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qprocessordetection.h
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// Copyright (C) 2016 The Qt Company Ltd.
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// Copyright (C) 2016 Intel Corporation.
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// SPDX-License-Identifier: LicenseRef-Qt-Commercial OR LGPL-3.0-only OR GPL-2.0-only OR GPL-3.0-only
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#if 0
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#pragma qt_class(QtProcessorDetection)
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#pragma qt_sync_skip_header_check
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#pragma qt_sync_stop_processing
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#endif
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#ifndef QPROCESSORDETECTION_H
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#define QPROCESSORDETECTION_H
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/*
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This file uses preprocessor #defines to set various Q_PROCESSOR_* #defines
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based on the following patterns:
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Q_PROCESSOR_{FAMILY}
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Q_PROCESSOR_{FAMILY}_{VARIANT}
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Q_PROCESSOR_{FAMILY}_{REVISION}
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The first is always defined. Defines for the various revisions/variants are
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optional and usually dependent on how the compiler was invoked. Variants
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that are a superset of another should have a define for the superset.
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In addition to the processor family, variants, and revisions, we also set
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Q_BYTE_ORDER appropriately for the target processor. For bi-endian
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processors, we try to auto-detect the byte order using the __BIG_ENDIAN__,
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__LITTLE_ENDIAN__, or __BYTE_ORDER__ preprocessor macros.
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Note: when adding support for new processors, be sure to update
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config.tests/arch/arch.cpp to ensure that configure can detect the target
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and host architectures.
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*/
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/* Machine byte-order, reuse preprocessor provided macros when available */
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#if defined(__ORDER_BIG_ENDIAN__)
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# define Q_BIG_ENDIAN __ORDER_BIG_ENDIAN__
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#else
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# define Q_BIG_ENDIAN 4321
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#endif
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#if defined(__ORDER_LITTLE_ENDIAN__)
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# define Q_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
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#else
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# define Q_LITTLE_ENDIAN 1234
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#endif
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/*
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Alpha family, no revisions or variants
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Alpha is bi-endian, use endianness auto-detection implemented below.
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*/
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#if defined(__alpha__) || defined(_M_ALPHA)
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# define Q_PROCESSOR_ALPHA
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// Q_BYTE_ORDER not defined, use endianness auto-detection
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/*
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ARM family, known revisions: V5, V6, V7, V8
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ARM is bi-endian, detect using __ARMEL__ or __ARMEB__, falling back to
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auto-detection implemented below.
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*/
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#elif defined(__arm__) || defined(__TARGET_ARCH_ARM) || defined(_M_ARM) || defined(_M_ARM64) || defined(__aarch64__) || defined(__ARM64__)
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# if defined(__aarch64__) || defined(__ARM64__) || defined(_M_ARM64)
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# define Q_PROCESSOR_ARM_64
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# define Q_PROCESSOR_WORDSIZE 8
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# else
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# define Q_PROCESSOR_ARM_32
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# endif
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# if defined(__ARM_ARCH) && __ARM_ARCH > 1
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# define Q_PROCESSOR_ARM __ARM_ARCH
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# elif defined(__TARGET_ARCH_ARM) && __TARGET_ARCH_ARM > 1
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# define Q_PROCESSOR_ARM __TARGET_ARCH_ARM
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# elif defined(_M_ARM) && _M_ARM > 1
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# define Q_PROCESSOR_ARM _M_ARM
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# elif defined(__ARM64_ARCH_8__) \
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|| defined(__aarch64__) \
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|| defined(__ARMv8__) \
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|| defined(__ARMv8_A__) \
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|| defined(_M_ARM64)
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# define Q_PROCESSOR_ARM 8
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# elif defined(__ARM_ARCH_7__) \
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|| defined(__ARM_ARCH_7A__) \
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|| defined(__ARM_ARCH_7R__) \
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|| defined(__ARM_ARCH_7M__) \
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|| defined(__ARM_ARCH_7S__) \
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|| defined(_ARM_ARCH_7) \
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|| defined(__CORE_CORTEXA__)
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# define Q_PROCESSOR_ARM 7
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# elif defined(__ARM_ARCH_6__) \
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|| defined(__ARM_ARCH_6J__) \
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|| defined(__ARM_ARCH_6T2__) \
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|| defined(__ARM_ARCH_6Z__) \
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|| defined(__ARM_ARCH_6K__) \
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|| defined(__ARM_ARCH_6ZK__) \
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|| defined(__ARM_ARCH_6M__)
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# define Q_PROCESSOR_ARM 6
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# elif defined(__ARM_ARCH_5TEJ__) \
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|| defined(__ARM_ARCH_5TE__)
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# define Q_PROCESSOR_ARM 5
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# else
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# define Q_PROCESSOR_ARM 0
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# endif
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# if Q_PROCESSOR_ARM >= 8
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# define Q_PROCESSOR_ARM_V8
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# endif
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# if Q_PROCESSOR_ARM >= 7
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# define Q_PROCESSOR_ARM_V7
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# endif
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# if Q_PROCESSOR_ARM >= 6
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# define Q_PROCESSOR_ARM_V6
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# endif
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# if Q_PROCESSOR_ARM >= 5
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# define Q_PROCESSOR_ARM_V5
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# else
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# error "ARM architecture too old"
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# endif
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# if defined(__ARMEL__) || defined(_M_ARM64)
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# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
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# elif defined(__ARMEB__)
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# define Q_BYTE_ORDER Q_BIG_ENDIAN
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# else
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// Q_BYTE_ORDER not defined, use endianness auto-detection
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#endif
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/*
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AVR32 family, no revisions or variants
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AVR32 is big-endian.
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*/
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// #elif defined(__avr32__)
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// # define Q_PROCESSOR_AVR32
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// # define Q_BYTE_ORDER Q_BIG_ENDIAN
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/*
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Blackfin family, no revisions or variants
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Blackfin is little-endian.
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*/
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// #elif defined(__bfin__)
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// # define Q_PROCESSOR_BLACKFIN
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// # define Q_BYTE_ORDER Q_LITTLE_ENDIAN
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/*
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PA-RISC family, no revisions or variants
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PA-RISC is big-endian.
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*/
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#elif defined(__hppa__)
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# define Q_PROCESSOR_HPPA
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# define Q_BYTE_ORDER Q_BIG_ENDIAN
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/*
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X86 family, known variants: 32- and 64-bit
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X86 is little-endian.
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*/
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#elif defined(__i386) || defined(__i386__) || defined(_M_IX86)
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# define Q_PROCESSOR_X86_32
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# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
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# define Q_PROCESSOR_WORDSIZE 4
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/*
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* We define Q_PROCESSOR_X86 == 6 for anything above a equivalent or better
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* than a Pentium Pro (the processor whose architecture was called P6) or an
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* Athlon.
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*
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* All processors since the Pentium III and the Athlon 4 have SSE support, so
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* we use that to detect. That leaves the original Athlon, Pentium Pro and
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* Pentium II.
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*/
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# if defined(_M_IX86)
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# define Q_PROCESSOR_X86 (_M_IX86/100)
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# elif defined(__i686__) || defined(__athlon__) || defined(__SSE__) || defined(__pentiumpro__)
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# define Q_PROCESSOR_X86 6
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# elif defined(__i586__) || defined(__k6__) || defined(__pentium__)
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# define Q_PROCESSOR_X86 5
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# elif defined(__i486__) || defined(__80486__)
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# define Q_PROCESSOR_X86 4
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# else
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# define Q_PROCESSOR_X86 3
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# endif
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#elif defined(__x86_64) || defined(__x86_64__) || defined(__amd64) || defined(_M_X64)
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# define Q_PROCESSOR_X86 6
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# define Q_PROCESSOR_X86_64
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# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
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# define Q_PROCESSOR_WORDSIZE 8
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/*
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Itanium (IA-64) family, no revisions or variants
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Itanium is bi-endian, use endianness auto-detection implemented below.
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*/
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#elif defined(__ia64) || defined(__ia64__) || defined(_M_IA64)
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# define Q_PROCESSOR_IA64
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# define Q_PROCESSOR_WORDSIZE 8
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// Q_BYTE_ORDER not defined, use endianness auto-detection
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/*
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LoongArch family, known variants: 32- and 64-bit
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LoongArch is little-endian.
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*/
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#elif defined(__loongarch__)
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# define Q_PROCESSOR_LOONGARCH
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# if __loongarch_grlen == 64
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# define Q_PROCESSOR_LOONGARCH_64
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# else
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# define Q_PROCESSOR_LOONGARCH_32
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# endif
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# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
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/*
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Motorola 68000 family, no revisions or variants
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M68K is big-endian.
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*/
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#elif defined(__m68k__)
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# define Q_PROCESSOR_M68K
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# define Q_BYTE_ORDER Q_BIG_ENDIAN
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/*
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MIPS family, known revisions: I, II, III, IV, 32, 64
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MIPS is bi-endian, use endianness auto-detection implemented below.
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*/
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#elif defined(__mips) || defined(__mips__) || defined(_M_MRX000)
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# define Q_PROCESSOR_MIPS
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# if defined(_MIPS_ARCH_MIPS1) || (defined(__mips) && __mips - 0 >= 1)
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# define Q_PROCESSOR_MIPS_I
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# endif
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# if defined(_MIPS_ARCH_MIPS2) || (defined(__mips) && __mips - 0 >= 2)
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# define Q_PROCESSOR_MIPS_II
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# endif
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# if defined(_MIPS_ARCH_MIPS3) || (defined(__mips) && __mips - 0 >= 3)
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# define Q_PROCESSOR_MIPS_III
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# endif
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# if defined(_MIPS_ARCH_MIPS4) || (defined(__mips) && __mips - 0 >= 4)
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# define Q_PROCESSOR_MIPS_IV
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# endif
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# if defined(_MIPS_ARCH_MIPS5) || (defined(__mips) && __mips - 0 >= 5)
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# define Q_PROCESSOR_MIPS_V
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# endif
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# if defined(_MIPS_ARCH_MIPS32) || defined(__mips32) || (defined(__mips) && __mips - 0 >= 32)
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# define Q_PROCESSOR_MIPS_32
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# endif
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# if defined(_MIPS_ARCH_MIPS64) || defined(__mips64)
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# define Q_PROCESSOR_MIPS_64
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# define Q_PROCESSOR_WORDSIZE 8
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# endif
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# if defined(__MIPSEL__)
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# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
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# elif defined(__MIPSEB__)
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# define Q_BYTE_ORDER Q_BIG_ENDIAN
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# else
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// Q_BYTE_ORDER not defined, use endianness auto-detection
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# endif
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/*
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Power family, known variants: 32- and 64-bit
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There are many more known variants/revisions that we do not handle/detect.
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See http://en.wikipedia.org/wiki/Power_Architecture
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and http://en.wikipedia.org/wiki/File:PowerISA-evolution.svg
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Power is bi-endian, use endianness auto-detection implemented below.
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*/
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#elif defined(__ppc__) || defined(__ppc) || defined(__powerpc__) \
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|| defined(_ARCH_COM) || defined(_ARCH_PWR) || defined(_ARCH_PPC) \
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|| defined(_M_MPPC) || defined(_M_PPC)
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# define Q_PROCESSOR_POWER
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# if defined(__ppc64__) || defined(__powerpc64__) || defined(__64BIT__)
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# define Q_PROCESSOR_POWER_64
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# define Q_PROCESSOR_WORDSIZE 8
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# else
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# define Q_PROCESSOR_POWER_32
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# endif
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// Q_BYTE_ORDER not defined, use endianness auto-detection
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/*
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RISC-V family, known variants: 32- and 64-bit
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RISC-V is little-endian.
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*/
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#elif defined(__riscv)
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# define Q_PROCESSOR_RISCV
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# if __riscv_xlen == 64
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# define Q_PROCESSOR_RISCV_64
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# else
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# define Q_PROCESSOR_RISCV_32
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# endif
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# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
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/*
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S390 family, known variant: S390X (64-bit)
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S390 is big-endian.
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*/
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#elif defined(__s390__)
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# define Q_PROCESSOR_S390
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# if defined(__s390x__)
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# define Q_PROCESSOR_S390_X
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# endif
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# define Q_BYTE_ORDER Q_BIG_ENDIAN
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/*
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SuperH family, optional revision: SH-4A
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SuperH is bi-endian, use endianness auto-detection implemented below.
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*/
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// #elif defined(__sh__)
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// # define Q_PROCESSOR_SH
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// # if defined(__sh4a__)
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// # define Q_PROCESSOR_SH_4A
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// # endif
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// Q_BYTE_ORDER not defined, use endianness auto-detection
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/*
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SPARC family, optional revision: V9
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SPARC is big-endian only prior to V9, while V9 is bi-endian with big-endian
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as the default byte order. Assume all SPARC systems are big-endian.
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*/
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#elif defined(__sparc__)
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# define Q_PROCESSOR_SPARC
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# if defined(__sparc_v9__) || defined(__sparcv9)
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# define Q_PROCESSOR_SPARC_V9
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# endif
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# if defined(__sparc64__)
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# define Q_PROCESSOR_SPARC_64
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# endif
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# define Q_BYTE_ORDER Q_BIG_ENDIAN
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// -- Web Assembly --
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#elif defined(__EMSCRIPTEN__)
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# define Q_PROCESSOR_WASM
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# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
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# define Q_PROCESSOR_WORDSIZE 8
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#ifdef QT_COMPILER_SUPPORTS_SSE2
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# define Q_PROCESSOR_X86 6
// enables SIMD support
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# define Q_PROCESSOR_X86_64
// wasm64
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# define Q_PROCESSOR_WASM_64
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#endif
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#endif
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/*
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NOTE:
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GCC 4.6 added __BYTE_ORDER__, __ORDER_BIG_ENDIAN__, __ORDER_LITTLE_ENDIAN__
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and __ORDER_PDP_ENDIAN__ in SVN r165881. If you are using GCC 4.6 or newer,
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this code will properly detect your target byte order; if you are not, and
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the __LITTLE_ENDIAN__ or __BIG_ENDIAN__ macros are not defined, then this
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code will fail to detect the target byte order.
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*/
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// Some processors support either endian format, try to detect which we are using.
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#if !defined(Q_BYTE_ORDER)
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# if defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == Q_BIG_ENDIAN || __BYTE_ORDER__ == Q_LITTLE_ENDIAN)
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// Reuse __BYTE_ORDER__ as-is, since our Q_*_ENDIAN #defines match the preprocessor defaults
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# define Q_BYTE_ORDER __BYTE_ORDER__
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# elif defined(__BIG_ENDIAN__) || defined(_big_endian__) || defined(_BIG_ENDIAN)
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# define Q_BYTE_ORDER Q_BIG_ENDIAN
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# elif defined(__LITTLE_ENDIAN__) || defined(_little_endian__) || defined(_LITTLE_ENDIAN)
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# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
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# else
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# error "Unable to determine byte order!"
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# endif
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#endif
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/*
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Size of a pointer and the machine register size. We detect a 64-bit system by:
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* GCC and compatible compilers (Clang, ICC on OS X and Windows) always define
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__SIZEOF_POINTER__. This catches all known cases of ILP32 builds on 64-bit
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processors.
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* Most other Unix compilers define __LP64__ or _LP64 on 64-bit mode
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(Long and Pointer 64-bit)
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* If Q_PROCESSOR_WORDSIZE was defined above, it's assumed to match the pointer
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size.
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Otherwise, we assume to be 32-bit and then check in qglobal.cpp that it is right.
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*/
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#if defined __SIZEOF_POINTER__
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# define QT_POINTER_SIZE __SIZEOF_POINTER__
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#elif defined(__LP64__) || defined(_LP64)
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# define QT_POINTER_SIZE 8
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#elif defined(Q_PROCESSOR_WORDSIZE)
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# define QT_POINTER_SIZE Q_PROCESSOR_WORDSIZE
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#else
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# define QT_POINTER_SIZE 4
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#endif
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/*
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Define Q_PROCESSOR_WORDSIZE to be the size of the machine's word (usually,
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the size of the register). On some architectures where a pointer could be
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smaller than the register, the macro is defined above.
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Falls back to QT_POINTER_SIZE if not set explicitly for the platform.
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*/
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#ifndef Q_PROCESSOR_WORDSIZE
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# define Q_PROCESSOR_WORDSIZE QT_POINTER_SIZE
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#endif
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#endif
// QPROCESSORDETECTION_H
qtbase
src
corelib
global
qprocessordetection.h
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