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qsimd_x86_p.h
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1// Copyright (C) 2022 Intel Corporation.
2// SPDX-License-Identifier: LicenseRef-Qt-Commercial OR LGPL-3.0-only OR GPL-2.0-only OR GPL-3.0-only
3// This is a generated file. DO NOT EDIT.
4// Please see util/x86simdgen/README.md
5
6//
7// W A R N I N G
8// -------------
9//
10// This file is not part of the Qt API. It exists purely as an
11// implementation detail. This header file may change from version to
12// version without notice, or even be removed.
13//
14// We mean it.
15//
16
17// This is a generated file. DO NOT EDIT.
18// Please see util/x86simdgen/README.md
19#ifndef QSIMD_X86_P_H
20#define QSIMD_X86_P_H
21
22#include <stdint.h>
23
24// in CPUID Leaf 1, EDX:
25#define cpu_feature_sse2 (UINT64_C(1) << 0)
26
27// in CPUID Leaf 1, ECX:
28#define cpu_feature_sse3 (UINT64_C(1) << 1)
29#define cpu_feature_ssse3 (UINT64_C(1) << 2)
30#define cpu_feature_fma (UINT64_C(1) << 3)
31#define cpu_feature_sse4_1 (UINT64_C(1) << 4)
32#define cpu_feature_sse4_2 (UINT64_C(1) << 5)
33#define cpu_feature_movbe (UINT64_C(1) << 6)
34#define cpu_feature_popcnt (UINT64_C(1) << 7)
35#define cpu_feature_aes (UINT64_C(1) << 8)
36#define cpu_feature_avx (UINT64_C(1) << 9)
37#define cpu_feature_f16c (UINT64_C(1) << 10)
38
39// in CPUID Leaf 7, Sub-leaf 0, EBX:
40#define cpu_feature_bmi (UINT64_C(1) << 11)
41#define cpu_feature_avx2 (UINT64_C(1) << 12)
42#define cpu_feature_bmi2 (UINT64_C(1) << 13)
43#define cpu_feature_avx512f (UINT64_C(1) << 14)
44#define cpu_feature_avx512dq (UINT64_C(1) << 15)
45#define cpu_feature_avx512ifma (UINT64_C(1) << 16)
46#define cpu_feature_avx512cd (UINT64_C(1) << 17)
47#define cpu_feature_sha (UINT64_C(1) << 18)
48#define cpu_feature_avx512bw (UINT64_C(1) << 19)
49#define cpu_feature_avx512vl (UINT64_C(1) << 20)
50
51// in CPUID Leaf 7, Sub-leaf 0, ECX:
52#define cpu_feature_avx512vbmi (UINT64_C(1) << 21)
53#define cpu_feature_waitpkg (UINT64_C(1) << 22)
54#define cpu_feature_avx512vbmi2 (UINT64_C(1) << 23)
55#define cpu_feature_shstk (UINT64_C(1) << 24)
56#define cpu_feature_gfni (UINT64_C(1) << 25)
57#define cpu_feature_vaes (UINT64_C(1) << 26)
58#define cpu_feature_avx512bitalg (UINT64_C(1) << 27)
59#define cpu_feature_avx512vpopcntdq (UINT64_C(1) << 28)
60
61// in CPUID Leaf 7, Sub-leaf 0, EDX:
62#define cpu_feature_hybrid (UINT64_C(1) << 29)
63#define cpu_feature_ibt (UINT64_C(1) << 30)
64#define cpu_feature_avx512fp16 (UINT64_C(1) << 31)
65
66// in CPUID Leaf 7, Sub-leaf 1, EAX:
67#define cpu_feature_raoint (UINT64_C(1) << 32)
68#define cpu_feature_cmpccxadd (UINT64_C(1) << 33)
69#define cpu_feature_avxifma (UINT64_C(1) << 34)
70#define cpu_feature_lam (UINT64_C(1) << 35)
71
72// CPU architectures
73#define cpu_x86_64 (0
75#define cpu_core2 (cpu_x86_64
82#define cpu_wsm (cpu_nhm)
83#define cpu_snb (cpu_wsm
85#define cpu_ivb (cpu_snb
93#define cpu_bdw (cpu_hsw)
94#define cpu_bdx (cpu_bdw)
95#define cpu_skl (cpu_bdw)
102#define cpu_clx (cpu_skx)
103#define cpu_cpx (cpu_clx)
113#define cpu_wlc (cpu_snc
116#define cpu_glc (cpu_wlc
118#define cpu_rpc (cpu_glc)
119#define cpu_rwc (cpu_rpc)
120#define cpu_slm (cpu_wsm
122#define cpu_glm (cpu_slm)
123#define cpu_tnt (cpu_glm
135#define cpu_cnl (cpu_plc)
136#define cpu_icl (cpu_snc)
137#define cpu_tgl (cpu_wlc)
138#define cpu_adl (cpu_grt)
139#define cpu_rpl (cpu_grt)
140#define cpu_mtl (cpu_cmt)
141#define cpu_arl (cpu_cmt)
142#define cpu_lnl (cpu_cmt)
143#define cpu_icx (cpu_snc)
144#define cpu_spr (cpu_glc)
145#define cpu_emr (cpu_spr)
146#define cpu_gnr (cpu_glc)
150#define cpu_grr (cpu_srf
152#define cpu_cwf (cpu_srf)
153#define cpu_nehalem (cpu_nhm)
154#define cpu_westmere (cpu_wsm)
155#define cpu_sandybridge (cpu_snb)
156#define cpu_ivybridge (cpu_ivb)
157#define cpu_haswell (cpu_hsw)
158#define cpu_broadwell (cpu_bdw)
159#define cpu_skylake (cpu_skl)
160#define cpu_skylake_avx512 (cpu_skx)
161#define cpu_cascadelake (cpu_clx)
162#define cpu_cooperlake (cpu_cpx)
163#define cpu_palmcove (cpu_plc)
164#define cpu_cannonlake (cpu_cnl)
165#define cpu_sunnycove (cpu_snc)
166#define cpu_icelake_client (cpu_icl)
167#define cpu_icelake_server (cpu_icx)
168#define cpu_willowcove (cpu_wlc)
169#define cpu_tigerlake (cpu_tgl)
170#define cpu_goldencove (cpu_glc)
171#define cpu_alderlake (cpu_adl)
172#define cpu_raptorcove (cpu_rpc)
173#define cpu_raptorlake (cpu_rpl)
174#define cpu_redwoodcove (cpu_rwc)
175#define cpu_meteorlake (cpu_mtl)
176#define cpu_arrowlake (cpu_arl)
177#define cpu_lunarlake (cpu_lnl)
178#define cpu_sapphirerapids (cpu_spr)
179#define cpu_emeraldrapids (cpu_emr)
180#define cpu_graniterapids (cpu_gnr)
181#define cpu_silvermont (cpu_slm)
182#define cpu_goldmont (cpu_glm)
183#define cpu_tremont (cpu_tnt)
184#define cpu_gracemont (cpu_grt)
185#define cpu_crestmont (cpu_cmt)
186#define cpu_grandridge (cpu_grr)
187#define cpu_sierraforest (cpu_srf)
188#define cpu_clearwaterforest (cpu_cwf)
189
190// __attribute__ target strings for GCC and Clang
191#define QT_FUNCTION_TARGET_STRING_SSE2 "sse2"
192#define QT_FUNCTION_TARGET_STRING_SSE3 "sse3"
193#define QT_FUNCTION_TARGET_STRING_SSSE3 "ssse3"
194#define QT_FUNCTION_TARGET_STRING_FMA "fma"
195#define QT_FUNCTION_TARGET_STRING_SSE4_1 "sse4.1"
196#define QT_FUNCTION_TARGET_STRING_SSE4_2 "sse4.2"
197#define QT_FUNCTION_TARGET_STRING_MOVBE "movbe"
198#define QT_FUNCTION_TARGET_STRING_POPCNT "popcnt"
199#define QT_FUNCTION_TARGET_STRING_AES "aes,sse4.2"
200#define QT_FUNCTION_TARGET_STRING_AVX "avx"
201#define QT_FUNCTION_TARGET_STRING_F16C "f16c,avx"
202#define QT_FUNCTION_TARGET_STRING_BMI "bmi"
203#define QT_FUNCTION_TARGET_STRING_AVX2 "avx2,avx"
204#define QT_FUNCTION_TARGET_STRING_BMI2 "bmi2"
205#define QT_FUNCTION_TARGET_STRING_AVX512F "avx512f,avx"
206#define QT_FUNCTION_TARGET_STRING_AVX512DQ "avx512dq,avx512f"
207#define QT_FUNCTION_TARGET_STRING_AVX512IFMA "avx512ifma,avx512f"
208#define QT_FUNCTION_TARGET_STRING_AVX512CD "avx512cd,avx512f"
209#define QT_FUNCTION_TARGET_STRING_SHA "sha"
210#define QT_FUNCTION_TARGET_STRING_AVX512BW "avx512bw,avx512f"
211#define QT_FUNCTION_TARGET_STRING_AVX512VL "avx512vl,avx512f"
212#define QT_FUNCTION_TARGET_STRING_AVX512VBMI "avx512vbmi,avx512f"
213#define QT_FUNCTION_TARGET_STRING_WAITPKG "waitpkg"
214#define QT_FUNCTION_TARGET_STRING_AVX512VBMI2 "avx512vbmi2,avx512f"
215#define QT_FUNCTION_TARGET_STRING_SHSTK "shstk"
216#define QT_FUNCTION_TARGET_STRING_GFNI "gfni"
217#define QT_FUNCTION_TARGET_STRING_VAES "vaes,avx2,avx,aes"
218#define QT_FUNCTION_TARGET_STRING_AVX512BITALG "avx512bitalg,avx512f"
219#define QT_FUNCTION_TARGET_STRING_AVX512VPOPCNTDQ "avx512vpopcntdq,avx512f"
220#define QT_FUNCTION_TARGET_STRING_HYBRID "hybrid"
221#define QT_FUNCTION_TARGET_STRING_IBT "ibt"
222#define QT_FUNCTION_TARGET_STRING_AVX512FP16 "avx512fp16,avx512f,f16c"
223#define QT_FUNCTION_TARGET_STRING_RAOINT "raoint"
224#define QT_FUNCTION_TARGET_STRING_CMPCCXADD "cmpccxadd"
225#define QT_FUNCTION_TARGET_STRING_AVXIFMA "avxifma,avx"
226#define QT_FUNCTION_TARGET_STRING_LAM "lam"
227#define QT_FUNCTION_TARGET_STRING_ARCH_X86_64 "sse2"
228#define QT_FUNCTION_TARGET_STRING_ARCH_CORE2 QT_FUNCTION_TARGET_STRING_ARCH_X86_64 ",sse3,ssse3,cx16"
229#define QT_FUNCTION_TARGET_STRING_ARCH_NHM QT_FUNCTION_TARGET_STRING_ARCH_CORE2 ",sse4.1,sse4.2,popcnt"
230#define QT_FUNCTION_TARGET_STRING_ARCH_WSM QT_FUNCTION_TARGET_STRING_ARCH_NHM
231#define QT_FUNCTION_TARGET_STRING_ARCH_SNB QT_FUNCTION_TARGET_STRING_ARCH_WSM ",avx"
232#define QT_FUNCTION_TARGET_STRING_ARCH_IVB QT_FUNCTION_TARGET_STRING_ARCH_SNB ",f16c,fsgsbase"
233#define QT_FUNCTION_TARGET_STRING_ARCH_HSW QT_FUNCTION_TARGET_STRING_ARCH_IVB ",avx2,fma,bmi,bmi2,lzcnt,movbe"
234#define QT_FUNCTION_TARGET_STRING_ARCH_BDW QT_FUNCTION_TARGET_STRING_ARCH_HSW ",adx"
235#define QT_FUNCTION_TARGET_STRING_ARCH_BDX QT_FUNCTION_TARGET_STRING_ARCH_BDW
236#define QT_FUNCTION_TARGET_STRING_ARCH_SKL QT_FUNCTION_TARGET_STRING_ARCH_BDW ",xsavec,xsaves"
237#define QT_FUNCTION_TARGET_STRING_ARCH_SKX QT_FUNCTION_TARGET_STRING_ARCH_SKL ",avx512f,avx512dq,avx512cd,avx512bw,avx512vl"
238#define QT_FUNCTION_TARGET_STRING_ARCH_CLX QT_FUNCTION_TARGET_STRING_ARCH_SKX ",avx512vnni"
239#define QT_FUNCTION_TARGET_STRING_ARCH_CPX QT_FUNCTION_TARGET_STRING_ARCH_CLX ",avx512bf16"
240#define QT_FUNCTION_TARGET_STRING_ARCH_PLC QT_FUNCTION_TARGET_STRING_ARCH_SKX ",avx512ifma,avx512vbmi"
241#define QT_FUNCTION_TARGET_STRING_ARCH_SNC QT_FUNCTION_TARGET_STRING_ARCH_PLC ",avx512vbmi2,gfni,vaes,vpclmulqdq,avx512vnni,avx512bitalg,avx512vpopcntdq"
242#define QT_FUNCTION_TARGET_STRING_ARCH_WLC QT_FUNCTION_TARGET_STRING_ARCH_SNC ",shstk,movdiri,movdir64b,ibt,keylocker"
243#define QT_FUNCTION_TARGET_STRING_ARCH_GLC QT_FUNCTION_TARGET_STRING_ARCH_WLC ",avx512bf16,avxvnni,cldemote,waitpkg,serialize,uintr"
244#define QT_FUNCTION_TARGET_STRING_ARCH_RPC QT_FUNCTION_TARGET_STRING_ARCH_GLC
245#define QT_FUNCTION_TARGET_STRING_ARCH_RWC QT_FUNCTION_TARGET_STRING_ARCH_RPC ",prefetchiti"
246#define QT_FUNCTION_TARGET_STRING_ARCH_SLM QT_FUNCTION_TARGET_STRING_ARCH_WSM ",rdrnd,movbe"
247#define QT_FUNCTION_TARGET_STRING_ARCH_GLM QT_FUNCTION_TARGET_STRING_ARCH_SLM ",fsgsbase,rdseed,lzcnt,xsavec,xsaves"
248#define QT_FUNCTION_TARGET_STRING_ARCH_TNT QT_FUNCTION_TARGET_STRING_ARCH_GLM ",clwb,gfni,cldemote,waitpkg,movdiri,movdir64b"
249#define QT_FUNCTION_TARGET_STRING_ARCH_GRT QT_FUNCTION_TARGET_STRING_ARCH_SKL ",avxvnni,gfni,vaes,vpclmulqdq,serialize,shstk,cldemote,movdiri,movdir64b,ibt,waitpkg,keylocker"
250#define QT_FUNCTION_TARGET_STRING_ARCH_CMT QT_FUNCTION_TARGET_STRING_ARCH_GRT ",cmpccxadd,avxifma,avxneconvert,avxvnniint8"
251#define QT_FUNCTION_TARGET_STRING_ARCH_CNL QT_FUNCTION_TARGET_STRING_ARCH_PLC
252#define QT_FUNCTION_TARGET_STRING_ARCH_ICL QT_FUNCTION_TARGET_STRING_ARCH_SNC
253#define QT_FUNCTION_TARGET_STRING_ARCH_TGL QT_FUNCTION_TARGET_STRING_ARCH_WLC
254#define QT_FUNCTION_TARGET_STRING_ARCH_ADL QT_FUNCTION_TARGET_STRING_ARCH_GRT
255#define QT_FUNCTION_TARGET_STRING_ARCH_RPL QT_FUNCTION_TARGET_STRING_ARCH_GRT
256#define QT_FUNCTION_TARGET_STRING_ARCH_MTL QT_FUNCTION_TARGET_STRING_ARCH_CMT
257#define QT_FUNCTION_TARGET_STRING_ARCH_ARL QT_FUNCTION_TARGET_STRING_ARCH_CMT
258#define QT_FUNCTION_TARGET_STRING_ARCH_LNL QT_FUNCTION_TARGET_STRING_ARCH_CMT
259#define QT_FUNCTION_TARGET_STRING_ARCH_ICX QT_FUNCTION_TARGET_STRING_ARCH_SNC ",pconfig"
260#define QT_FUNCTION_TARGET_STRING_ARCH_SPR QT_FUNCTION_TARGET_STRING_ARCH_GLC ",pconfig,amx-tile,amx-bf16,amx-int8"
261#define QT_FUNCTION_TARGET_STRING_ARCH_EMR QT_FUNCTION_TARGET_STRING_ARCH_SPR
262#define QT_FUNCTION_TARGET_STRING_ARCH_GNR QT_FUNCTION_TARGET_STRING_ARCH_GLC ",pconfig,amx-tile,amx-bf16,amx-int8,amx-fp16,amx-complex"
263#define QT_FUNCTION_TARGET_STRING_ARCH_SRF QT_FUNCTION_TARGET_STRING_ARCH_CMT ",cmpccxadd,avxifma,avxneconvert,avxvnniint8"
264#define QT_FUNCTION_TARGET_STRING_ARCH_GRR QT_FUNCTION_TARGET_STRING_ARCH_SRF ",raoint"
265#define QT_FUNCTION_TARGET_STRING_ARCH_CWF QT_FUNCTION_TARGET_STRING_ARCH_SRF
266#define QT_FUNCTION_TARGET_STRING_ARCH_NEHALEM QT_FUNCTION_TARGET_STRING_ARCH_NHM
267#define QT_FUNCTION_TARGET_STRING_ARCH_WESTMERE QT_FUNCTION_TARGET_STRING_ARCH_WSM
268#define QT_FUNCTION_TARGET_STRING_ARCH_SANDYBRIDGE QT_FUNCTION_TARGET_STRING_ARCH_SNB
269#define QT_FUNCTION_TARGET_STRING_ARCH_IVYBRIDGE QT_FUNCTION_TARGET_STRING_ARCH_IVB
270#define QT_FUNCTION_TARGET_STRING_ARCH_HASWELL QT_FUNCTION_TARGET_STRING_ARCH_HSW
271#define QT_FUNCTION_TARGET_STRING_ARCH_BROADWELL QT_FUNCTION_TARGET_STRING_ARCH_BDW
272#define QT_FUNCTION_TARGET_STRING_ARCH_SKYLAKE QT_FUNCTION_TARGET_STRING_ARCH_SKL
273#define QT_FUNCTION_TARGET_STRING_ARCH_SKYLAKE_AVX512 QT_FUNCTION_TARGET_STRING_ARCH_SKX
274#define QT_FUNCTION_TARGET_STRING_ARCH_CASCADELAKE QT_FUNCTION_TARGET_STRING_ARCH_CLX
275#define QT_FUNCTION_TARGET_STRING_ARCH_COOPERLAKE QT_FUNCTION_TARGET_STRING_ARCH_CPX
276#define QT_FUNCTION_TARGET_STRING_ARCH_PALMCOVE QT_FUNCTION_TARGET_STRING_ARCH_PLC
277#define QT_FUNCTION_TARGET_STRING_ARCH_CANNONLAKE QT_FUNCTION_TARGET_STRING_ARCH_CNL
278#define QT_FUNCTION_TARGET_STRING_ARCH_SUNNYCOVE QT_FUNCTION_TARGET_STRING_ARCH_SNC
279#define QT_FUNCTION_TARGET_STRING_ARCH_ICELAKE_CLIENT QT_FUNCTION_TARGET_STRING_ARCH_ICL
280#define QT_FUNCTION_TARGET_STRING_ARCH_ICELAKE_SERVER QT_FUNCTION_TARGET_STRING_ARCH_ICX
281#define QT_FUNCTION_TARGET_STRING_ARCH_WILLOWCOVE QT_FUNCTION_TARGET_STRING_ARCH_WLC
282#define QT_FUNCTION_TARGET_STRING_ARCH_TIGERLAKE QT_FUNCTION_TARGET_STRING_ARCH_TGL
283#define QT_FUNCTION_TARGET_STRING_ARCH_GOLDENCOVE QT_FUNCTION_TARGET_STRING_ARCH_GLC
284#define QT_FUNCTION_TARGET_STRING_ARCH_ALDERLAKE QT_FUNCTION_TARGET_STRING_ARCH_ADL
285#define QT_FUNCTION_TARGET_STRING_ARCH_RAPTORCOVE QT_FUNCTION_TARGET_STRING_ARCH_RPC
286#define QT_FUNCTION_TARGET_STRING_ARCH_RAPTORLAKE QT_FUNCTION_TARGET_STRING_ARCH_RPL
287#define QT_FUNCTION_TARGET_STRING_ARCH_REDWOODCOVE QT_FUNCTION_TARGET_STRING_ARCH_RWC
288#define QT_FUNCTION_TARGET_STRING_ARCH_METEORLAKE QT_FUNCTION_TARGET_STRING_ARCH_MTL
289#define QT_FUNCTION_TARGET_STRING_ARCH_ARROWLAKE QT_FUNCTION_TARGET_STRING_ARCH_ARL
290#define QT_FUNCTION_TARGET_STRING_ARCH_LUNARLAKE QT_FUNCTION_TARGET_STRING_ARCH_LNL
291#define QT_FUNCTION_TARGET_STRING_ARCH_SAPPHIRERAPIDS QT_FUNCTION_TARGET_STRING_ARCH_SPR
292#define QT_FUNCTION_TARGET_STRING_ARCH_EMERALDRAPIDS QT_FUNCTION_TARGET_STRING_ARCH_EMR
293#define QT_FUNCTION_TARGET_STRING_ARCH_GRANITERAPIDS QT_FUNCTION_TARGET_STRING_ARCH_GNR
294#define QT_FUNCTION_TARGET_STRING_ARCH_SILVERMONT QT_FUNCTION_TARGET_STRING_ARCH_SLM
295#define QT_FUNCTION_TARGET_STRING_ARCH_GOLDMONT QT_FUNCTION_TARGET_STRING_ARCH_GLM
296#define QT_FUNCTION_TARGET_STRING_ARCH_TREMONT QT_FUNCTION_TARGET_STRING_ARCH_TNT
297#define QT_FUNCTION_TARGET_STRING_ARCH_GRACEMONT QT_FUNCTION_TARGET_STRING_ARCH_GRT
298#define QT_FUNCTION_TARGET_STRING_ARCH_CRESTMONT QT_FUNCTION_TARGET_STRING_ARCH_CMT
299#define QT_FUNCTION_TARGET_STRING_ARCH_GRANDRIDGE QT_FUNCTION_TARGET_STRING_ARCH_GRR
300#define QT_FUNCTION_TARGET_STRING_ARCH_SIERRAFOREST QT_FUNCTION_TARGET_STRING_ARCH_SRF
301#define QT_FUNCTION_TARGET_STRING_ARCH_CLEARWATERFOREST QT_FUNCTION_TARGET_STRING_ARCH_CWF
302
303static const uint64_t _compilerCpuFeatures = 0
304#ifdef __SSE2__
306#endif
307#ifdef __SSE3__
308 | cpu_feature_sse3
309#endif
310#ifdef __SSSE3__
311 | cpu_feature_ssse3
312#endif
313#ifdef __FMA__
314 | cpu_feature_fma
315#endif
316#ifdef __SSE4_1__
317 | cpu_feature_sse4_1
318#endif
319#ifdef __SSE4_2__
320 | cpu_feature_sse4_2
321#endif
322#ifdef __MOVBE__
323 | cpu_feature_movbe
324#endif
325#ifdef __POPCNT__
326 | cpu_feature_popcnt
327#endif
328#ifdef __AES__
329 | cpu_feature_aes
330#endif
331#ifdef __AVX__
332 | cpu_feature_avx
333#endif
334#ifdef __F16C__
335 | cpu_feature_f16c
336#endif
337#ifdef __BMI__
338 | cpu_feature_bmi
339#endif
340#ifdef __AVX2__
341 | cpu_feature_avx2
342#endif
343#ifdef __BMI2__
344 | cpu_feature_bmi2
345#endif
346#ifdef __AVX512F__
347 | cpu_feature_avx512f
348#endif
349#ifdef __AVX512DQ__
350 | cpu_feature_avx512dq
351#endif
352#ifdef __AVX512IFMA__
353 | cpu_feature_avx512ifma
354#endif
355#ifdef __AVX512CD__
356 | cpu_feature_avx512cd
357#endif
358#ifdef __SHA__
359 | cpu_feature_sha
360#endif
361#ifdef __AVX512BW__
362 | cpu_feature_avx512bw
363#endif
364#ifdef __AVX512VL__
365 | cpu_feature_avx512vl
366#endif
367#ifdef __AVX512VBMI__
368 | cpu_feature_avx512vbmi
369#endif
370#ifdef __WAITPKG__
371 | cpu_feature_waitpkg
372#endif
373#ifdef __AVX512VBMI2__
374 | cpu_feature_avx512vbmi2
375#endif
376#ifdef __SHSTK__
377 | cpu_feature_shstk
378#endif
379#ifdef __GFNI__
380 | cpu_feature_gfni
381#endif
382#ifdef __VAES__
383 | cpu_feature_vaes
384#endif
385#ifdef __AVX512BITALG__
386 | cpu_feature_avx512bitalg
387#endif
388#ifdef __AVX512VPOPCNTDQ__
389 | cpu_feature_avx512vpopcntdq
390#endif
391#ifdef __HYBRID__
392 | cpu_feature_hybrid
393#endif
394#ifdef __IBT__
395 | cpu_feature_ibt
396#endif
397#ifdef __AVX512FP16__
398 | cpu_feature_avx512fp16
399#endif
400#ifdef __RAOINT__
401 | cpu_feature_raoint
402#endif
403#ifdef __CMPCCXADD__
404 | cpu_feature_cmpccxadd
405#endif
406#ifdef __AVXIFMA__
407 | cpu_feature_avxifma
408#endif
409#ifdef __LAM__
410 | cpu_feature_lam
411#endif
412 ;
413
414#if (defined __cplusplus) && __cplusplus >= 201103L
415enum X86CpuFeatures : uint64_t {
416 CpuFeatureSSE2 = cpu_feature_sse2, ///< Streaming SIMD Extensions 2
417 CpuFeatureSSE3 = cpu_feature_sse3, ///< Streaming SIMD Extensions 3
418 CpuFeatureSSSE3 = cpu_feature_ssse3, ///< Supplemental Streaming SIMD Extensions 3
419 CpuFeatureFMA = cpu_feature_fma, ///< Fused Multiply-Add
420 CpuFeatureSSE4_1 = cpu_feature_sse4_1, ///< Streaming SIMD Extensions 4.1
421 CpuFeatureSSE4_2 = cpu_feature_sse4_2, ///< Streaming SIMD Extensions 4.2
422 CpuFeatureMOVBE = cpu_feature_movbe, ///< MOV Big Endian
423 CpuFeaturePOPCNT = cpu_feature_popcnt, ///< Population count
424 CpuFeatureAES = cpu_feature_aes, ///< Advenced Encryption Standard
425 CpuFeatureAVX = cpu_feature_avx, ///< Advanced Vector Extensions
426 CpuFeatureF16C = cpu_feature_f16c, ///< 16-bit Float Conversion
427 CpuFeatureBMI = cpu_feature_bmi, ///< Bit Manipulation Instructions
428 CpuFeatureAVX2 = cpu_feature_avx2, ///< Advanced Vector Extensions 2
429 CpuFeatureBMI2 = cpu_feature_bmi2, ///< Bit Manipulation Instructions 2
430 CpuFeatureAVX512F = cpu_feature_avx512f, ///< AVX512 Foundation
431 CpuFeatureAVX512DQ = cpu_feature_avx512dq, ///< AVX512 Double & Quadword
432 CpuFeatureAVX512IFMA = cpu_feature_avx512ifma, ///< AVX512 Integer Fused Multiply-Add
433 CpuFeatureAVX512CD = cpu_feature_avx512cd, ///< AVX512 Conflict Detection
434 CpuFeatureSHA = cpu_feature_sha, ///< SHA-1 and SHA-256 instructions
435 CpuFeatureAVX512BW = cpu_feature_avx512bw, ///< AVX512 Byte & Word
436 CpuFeatureAVX512VL = cpu_feature_avx512vl, ///< AVX512 Vector Length
437 CpuFeatureAVX512VBMI = cpu_feature_avx512vbmi, ///< AVX512 Vector Byte Manipulation Instructions
438 CpuFeatureWAITPKG = cpu_feature_waitpkg, ///< User-Level Monitor / Wait
439 CpuFeatureAVX512VBMI2 = cpu_feature_avx512vbmi2, ///< AVX512 Vector Byte Manipulation Instructions 2
440 CpuFeatureSHSTK = cpu_feature_shstk, ///< Control Flow Enforcement Technology Shadow Stack
441 CpuFeatureGFNI = cpu_feature_gfni, ///< Galois Field new instructions
442 CpuFeatureVAES = cpu_feature_vaes, ///< 256- and 512-bit AES
443 CpuFeatureAVX512BITALG = cpu_feature_avx512bitalg, ///< AVX512 Bit Algorithms
444 CpuFeatureAVX512VPOPCNTDQ = cpu_feature_avx512vpopcntdq, ///< AVX512 Population Count
445 CpuFeatureHYBRID = cpu_feature_hybrid, ///< Hybrid processor
446 CpuFeatureIBT = cpu_feature_ibt, ///< Control Flow Enforcement Technology Indirect Branch Tracking
447 CpuFeatureAVX512FP16 = cpu_feature_avx512fp16, ///< AVX512 16-bit Floating Point
448 CpuFeatureRAOINT = cpu_feature_raoint, ///< Remote Atomic Operations, Integer
449 CpuFeatureCMPCCXADD = cpu_feature_cmpccxadd, ///< CMPccXADD instructions
450 CpuFeatureAVXIFMA = cpu_feature_avxifma, ///< AVX-IFMA instructions
451 CpuFeatureLAM = cpu_feature_lam, ///< Linear Address Masking
452}; // enum X86CpuFeatures
453
454enum X86CpuArchitectures : uint64_t {
455 CpuArchx8664 = cpu_x86_64,
456 CpuArchCore2 = cpu_core2,
457 CpuArchNHM = cpu_nhm,
458 CpuArchWSM = cpu_wsm,
459 CpuArchSNB = cpu_snb,
460 CpuArchIVB = cpu_ivb, ///< rdrnd
461 CpuArchHSW = cpu_hsw, ///< hle,rtm
462 CpuArchBDW = cpu_bdw, ///< rdseed
463 CpuArchBDX = cpu_bdx,
464 CpuArchSKL = cpu_skl,
465 CpuArchSKX = cpu_skx, ///< clwb
466 CpuArchCLX = cpu_clx,
467 CpuArchCPX = cpu_cpx,
468 CpuArchPLC = cpu_plc, ///< sha
469 CpuArchSNC = cpu_snc, ///< fsrm,rdpid
470 CpuArchWLC = cpu_wlc, ///< avx512vp2intersect
471 CpuArchGLC = cpu_glc, ///< tsxldtrk
472 CpuArchRPC = cpu_rpc,
473 CpuArchRWC = cpu_rwc,
474 CpuArchSLM = cpu_slm,
475 CpuArchGLM = cpu_glm,
476 CpuArchTNT = cpu_tnt,
477 CpuArchGRT = cpu_grt, ///< rdpid
478 CpuArchCMT = cpu_cmt,
479 CpuArchCNL = cpu_cnl,
480 CpuArchICL = cpu_icl,
481 CpuArchTGL = cpu_tgl,
482 CpuArchADL = cpu_adl,
483 CpuArchRPL = cpu_rpl,
484 CpuArchMTL = cpu_mtl,
485 CpuArchARL = cpu_arl,
486 CpuArchLNL = cpu_lnl,
487 CpuArchICX = cpu_icx,
488 CpuArchSPR = cpu_spr,
489 CpuArchEMR = cpu_emr,
490 CpuArchGNR = cpu_gnr,
491 CpuArchSRF = cpu_srf,
492 CpuArchGRR = cpu_grr,
493 CpuArchCWF = cpu_cwf,
494 CpuArchNehalem = cpu_nehalem, ///< Intel Core i3/i5/i7
495 CpuArchWestmere = cpu_westmere, ///< Intel Core i3/i5/i7
496 CpuArchSandyBridge = cpu_sandybridge, ///< Second Generation Intel Core i3/i5/i7
497 CpuArchIvyBridge = cpu_ivybridge, ///< Third Generation Intel Core i3/i5/i7
498 CpuArchHaswell = cpu_haswell, ///< Fourth Generation Intel Core i3/i5/i7
499 CpuArchBroadwell = cpu_broadwell, ///< Fifth Generation Intel Core i3/i5/i7
500 CpuArchSkylake = cpu_skylake, ///< Sixth Generation Intel Core i3/i5/i7
501 CpuArchSkylakeAvx512 = cpu_skylake_avx512, ///< Intel Xeon Scalable
502 CpuArchCascadeLake = cpu_cascadelake, ///< Second Generation Intel Xeon Scalable
503 CpuArchCooperLake = cpu_cooperlake, ///< Third Generation Intel Xeon Scalable
504 CpuArchPalmCove = cpu_palmcove,
505 CpuArchCannonLake = cpu_cannonlake, ///< Intel Core i3-8121U
506 CpuArchSunnyCove = cpu_sunnycove,
507 CpuArchIceLakeClient = cpu_icelake_client, ///< Tenth Generation Intel Core i3/i5/i7
508 CpuArchIceLakeServer = cpu_icelake_server, ///< Third Generation Intel Xeon Scalable
509 CpuArchWillowCove = cpu_willowcove,
510 CpuArchTigerLake = cpu_tigerlake, ///< Eleventh Generation Intel Core i3/i5/i7
511 CpuArchGoldenCove = cpu_goldencove,
512 CpuArchAlderLake = cpu_alderlake, ///< Twelfth Generation Intel Core
513 CpuArchRaptorCove = cpu_raptorcove,
514 CpuArchRaptorLake = cpu_raptorlake, ///< Thirteenth Generation Intel Core
515 CpuArchRedwoodCove = cpu_redwoodcove,
516 CpuArchMeteorLake = cpu_meteorlake,
517 CpuArchArrowLake = cpu_arrowlake,
518 CpuArchLunarLake = cpu_lunarlake,
519 CpuArchSapphireRapids = cpu_sapphirerapids, ///< Fourth Generation Intel Xeon Scalable
520 CpuArchEmeraldRapids = cpu_emeraldrapids, ///< Fifth Generation Intel Xeon Scalable
521 CpuArchGraniteRapids = cpu_graniterapids,
522 CpuArchSilvermont = cpu_silvermont,
523 CpuArchGoldmont = cpu_goldmont,
524 CpuArchTremont = cpu_tremont,
525 CpuArchGracemont = cpu_gracemont,
526 CpuArchCrestmont = cpu_crestmont,
527 CpuArchGrandRidge = cpu_grandridge,
528 CpuArchSierraForest = cpu_sierraforest,
529 CpuArchClearwaterForest = cpu_clearwaterforest,
530}; // enum X86cpuArchitectures
531#endif /* C++11 */
532
533#endif /* QSIMD_X86_P_H */
XSaveBits
@ XSave_Bndcsr
@ XSave_X87
@ XSave_HwpState
@ XSave_AvxState
@ XSave_Xtilecfg
@ XSave_Xtiledata
@ XSave_Avx512State
@ XSave_AmxState
@ XSave_SseState
@ XSave_HdcState
@ XSave_PKRUState
@ XSave_OpMask
@ XSave_CetUState
@ XSave_Zmm_Hi256
@ XSave_CetState
@ XSave_Bndregs
@ XSave_UintrState
@ XSave_PTState
@ XSave_Ymm_Hi128
@ XSave_CetSState
@ XSave_Hi16_Zmm
@ XSave_MPXState
static const struct X86Architecture x86_architectures[]
X86CpuidLeaves
Definition qsimd_x86.cpp:55
@ Leaf01EDX
Definition qsimd_x86.cpp:56
@ Leaf07_01EAX
Definition qsimd_x86.cpp:61
@ Leaf07_00ECX
Definition qsimd_x86.cpp:59
@ Leaf80000008hEBX
Definition qsimd_x86.cpp:65
@ Leaf07_00EBX
Definition qsimd_x86.cpp:58
@ Leaf07_00EDX
Definition qsimd_x86.cpp:60
@ Leaf13_01EAX
Definition qsimd_x86.cpp:63
@ X86CpuidMaxLeaf
Definition qsimd_x86.cpp:66
@ Leaf07_01EDX
Definition qsimd_x86.cpp:62
@ Leaf01ECX
Definition qsimd_x86.cpp:57
@ Leaf80000001hECX
Definition qsimd_x86.cpp:64
static const uint16_t x86_locators[]
Definition qsimd_x86.cpp:69
static const uint64_t XSaveReq_AvxState
static const uint16_t features_indices[]
Definition qsimd_x86.cpp:47
static const char features_string[]
Definition qsimd_x86.cpp:8
static const uint64_t XSaveReq_CetState
static const struct XSaveRequirementMapping xsave_requirements[]
static const uint64_t XSaveReq_Avx512State
#define cpu_skx
Definition qsimd_x86_p.h:96
#define cpu_lunarlake
#define cpu_raptorlake
#define QT_FUNCTION_TARGET_STRING_ARCH_LNL
#define cpu_feature_gfni
Definition qsimd_x86_p.h:56
#define cpu_spr
#define cpu_rpl
#define cpu_haswell
#define QT_FUNCTION_TARGET_STRING_ARCH_ICL
#define cpu_feature_bmi2
Definition qsimd_x86_p.h:42
#define cpu_feature_bmi
Definition qsimd_x86_p.h:40
#define QT_FUNCTION_TARGET_STRING_ARCH_CORE2
static const uint64_t _compilerCpuFeatures
#define cpu_feature_waitpkg
Definition qsimd_x86_p.h:53
#define cpu_cwf
#define cpu_feature_avx
Definition qsimd_x86_p.h:36
#define cpu_sierraforest
#define cpu_westmere
#define cpu_redwoodcove
#define QT_FUNCTION_TARGET_STRING_ARCH_IVB
#define QT_FUNCTION_TARGET_STRING_ARCH_HSW
#define cpu_alderlake
#define QT_FUNCTION_TARGET_STRING_ARCH_EMR
#define cpu_rpc
#define cpu_feature_fma
Definition qsimd_x86_p.h:30
#define QT_FUNCTION_TARGET_STRING_ARCH_CLX
#define cpu_skylake
#define cpu_feature_sse4_2
Definition qsimd_x86_p.h:32
#define cpu_feature_shstk
Definition qsimd_x86_p.h:55
#define QT_FUNCTION_TARGET_STRING_ARCH_ICX
#define cpu_srf
#define cpu_tgl
#define cpu_feature_ssse3
Definition qsimd_x86_p.h:29
#define cpu_icelake_server
#define cpu_skl
Definition qsimd_x86_p.h:95
#define cpu_arl
#define cpu_meteorlake
#define cpu_feature_avx512ifma
Definition qsimd_x86_p.h:45
#define cpu_gracemont
#define cpu_feature_avx512vpopcntdq
Definition qsimd_x86_p.h:59
#define cpu_graniterapids
#define cpu_feature_avx512f
Definition qsimd_x86_p.h:43
#define cpu_snb
Definition qsimd_x86_p.h:83
#define cpu_feature_sha
Definition qsimd_x86_p.h:47
#define cpu_clearwaterforest
#define cpu_icelake_client
#define cpu_cannonlake
#define cpu_gnr
#define cpu_willowcove
#define cpu_feature_avx2
Definition qsimd_x86_p.h:41
#define cpu_cmt
#define QT_FUNCTION_TARGET_STRING_ARCH_WSM
#define cpu_feature_aes
Definition qsimd_x86_p.h:35
#define cpu_bdw
Definition qsimd_x86_p.h:93
#define cpu_grr
#define cpu_feature_vaes
Definition qsimd_x86_p.h:57
#define cpu_core2
Definition qsimd_x86_p.h:75
#define cpu_feature_avx512vl
Definition qsimd_x86_p.h:49
#define QT_FUNCTION_TARGET_STRING_ARCH_GLM
#define QT_FUNCTION_TARGET_STRING_ARCH_MTL
#define cpu_slm
#define cpu_wlc
#define cpu_feature_cmpccxadd
Definition qsimd_x86_p.h:68
#define cpu_feature_lam
Definition qsimd_x86_p.h:70
#define cpu_cooperlake
#define QT_FUNCTION_TARGET_STRING_ARCH_X86_64
#define cpu_feature_sse3
Definition qsimd_x86_p.h:28
#define cpu_sunnycove
#define cpu_x86_64
Definition qsimd_x86_p.h:73
#define cpu_feature_avx512bitalg
Definition qsimd_x86_p.h:58
#define cpu_feature_sse2
Definition qsimd_x86_p.h:25
#define cpu_ivybridge
#define QT_FUNCTION_TARGET_STRING_ARCH_TNT
#define cpu_wsm
Definition qsimd_x86_p.h:82
#define cpu_feature_avx512dq
Definition qsimd_x86_p.h:44
#define cpu_lnl
#define QT_FUNCTION_TARGET_STRING_ARCH_RWC
#define QT_FUNCTION_TARGET_STRING_ARCH_CWF
#define cpu_grandridge
#define cpu_rwc
#define cpu_snc
#define QT_FUNCTION_TARGET_STRING_ARCH_GLC
#define QT_FUNCTION_TARGET_STRING_ARCH_CNL
#define QT_FUNCTION_TARGET_STRING_ARCH_CMT
#define cpu_icl
#define cpu_emeraldrapids
#define cpu_glm
#define cpu_cpx
#define QT_FUNCTION_TARGET_STRING_ARCH_PLC
#define QT_FUNCTION_TARGET_STRING_ARCH_GNR
#define cpu_grt
#define cpu_plc
#define cpu_feature_raoint
Definition qsimd_x86_p.h:67
#define QT_FUNCTION_TARGET_STRING_ARCH_WLC
#define cpu_tigerlake
#define cpu_clx
#define QT_FUNCTION_TARGET_STRING_ARCH_ARL
#define cpu_cascadelake
#define QT_FUNCTION_TARGET_STRING_ARCH_SNC
#define cpu_tnt
#define QT_FUNCTION_TARGET_STRING_ARCH_BDW
#define cpu_tremont
#define QT_FUNCTION_TARGET_STRING_ARCH_RPL
#define cpu_glc
#define cpu_nhm
Definition qsimd_x86_p.h:78
#define QT_FUNCTION_TARGET_STRING_ARCH_SLM
#define cpu_feature_ibt
Definition qsimd_x86_p.h:63
#define cpu_feature_f16c
Definition qsimd_x86_p.h:37
#define QT_FUNCTION_TARGET_STRING_ARCH_GRR
#define QT_FUNCTION_TARGET_STRING_ARCH_GRT
#define QT_FUNCTION_TARGET_STRING_ARCH_SKX
#define cpu_goldencove
#define cpu_feature_avx512vbmi2
Definition qsimd_x86_p.h:54
#define cpu_skylake_avx512
#define cpu_feature_avx512fp16
Definition qsimd_x86_p.h:64
#define QT_FUNCTION_TARGET_STRING_ARCH_RPC
#define cpu_nehalem
#define cpu_feature_avxifma
Definition qsimd_x86_p.h:69
#define QT_FUNCTION_TARGET_STRING_ARCH_SRF
#define cpu_emr
#define cpu_icx
#define cpu_adl
#define cpu_cnl
#define cpu_feature_avx512bw
Definition qsimd_x86_p.h:48
#define cpu_palmcove
#define cpu_bdx
Definition qsimd_x86_p.h:94
#define QT_FUNCTION_TARGET_STRING_ARCH_SKL
#define QT_FUNCTION_TARGET_STRING_ARCH_CPX
#define cpu_feature_sse4_1
Definition qsimd_x86_p.h:31
#define QT_FUNCTION_TARGET_STRING_ARCH_SPR
#define QT_FUNCTION_TARGET_STRING_ARCH_TGL
#define cpu_feature_hybrid
Definition qsimd_x86_p.h:62
#define cpu_sandybridge
#define cpu_crestmont
#define cpu_goldmont
#define cpu_arrowlake
#define cpu_silvermont
#define QT_FUNCTION_TARGET_STRING_ARCH_SNB
#define cpu_broadwell
#define cpu_feature_popcnt
Definition qsimd_x86_p.h:34
#define cpu_mtl
#define cpu_hsw
Definition qsimd_x86_p.h:87
#define cpu_feature_movbe
Definition qsimd_x86_p.h:33
#define QT_FUNCTION_TARGET_STRING_ARCH_ADL
#define cpu_raptorcove
#define QT_FUNCTION_TARGET_STRING_ARCH_NHM
#define cpu_ivb
Definition qsimd_x86_p.h:85
#define cpu_feature_avx512vbmi
Definition qsimd_x86_p.h:52
#define cpu_feature_avx512cd
Definition qsimd_x86_p.h:46
#define cpu_sapphirerapids
uint64_t features
char name[17+1]