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qsimd_x86_p.h
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1// Copyright (C) 2022 Intel Corporation.
2// SPDX-License-Identifier: LicenseRef-Qt-Commercial OR LGPL-3.0-only OR GPL-2.0-only OR GPL-3.0-only
3// This is a generated file. DO NOT EDIT.
4// Please see util/x86simdgen/README.md
5
6//
7// W A R N I N G
8// -------------
9//
10// This file is not part of the Qt API. It exists purely as an
11// implementation detail. This header file may change from version to
12// version without notice, or even be removed.
13//
14// We mean it.
15//
16
17// This is a generated file. DO NOT EDIT.
18// Please see util/x86simdgen/README.md
19// Qt-Security score:significant reason:default
20#ifndef QSIMD_X86_P_H
21#define QSIMD_X86_P_H
22
23#include <stdint.h>
24
25// in CPUID Leaf 1, EDX:
26#define cpu_feature_sse2 (UINT64_C(1) << 0)
27
28// in CPUID Leaf 1, ECX:
29#define cpu_feature_sse3 (UINT64_C(1) << 1)
30#define cpu_feature_ssse3 (UINT64_C(1) << 2)
31#define cpu_feature_fma (UINT64_C(1) << 3)
32#define cpu_feature_sse4_1 (UINT64_C(1) << 4)
33#define cpu_feature_sse4_2 (UINT64_C(1) << 5)
34#define cpu_feature_movbe (UINT64_C(1) << 6)
35#define cpu_feature_popcnt (UINT64_C(1) << 7)
36#define cpu_feature_aes (UINT64_C(1) << 8)
37#define cpu_feature_avx (UINT64_C(1) << 9)
38#define cpu_feature_f16c (UINT64_C(1) << 10)
39
40// in CPUID Leaf 7, Sub-leaf 0, EBX:
41#define cpu_feature_bmi (UINT64_C(1) << 11)
42#define cpu_feature_avx2 (UINT64_C(1) << 12)
43#define cpu_feature_bmi2 (UINT64_C(1) << 13)
44#define cpu_feature_avx512f (UINT64_C(1) << 14)
45#define cpu_feature_avx512dq (UINT64_C(1) << 15)
46#define cpu_feature_avx512ifma (UINT64_C(1) << 16)
47#define cpu_feature_avx512cd (UINT64_C(1) << 17)
48#define cpu_feature_sha (UINT64_C(1) << 18)
49#define cpu_feature_avx512bw (UINT64_C(1) << 19)
50#define cpu_feature_avx512vl (UINT64_C(1) << 20)
51
52// in CPUID Leaf 7, Sub-leaf 0, ECX:
53#define cpu_feature_avx512vbmi (UINT64_C(1) << 21)
54#define cpu_feature_waitpkg (UINT64_C(1) << 22)
55#define cpu_feature_avx512vbmi2 (UINT64_C(1) << 23)
56#define cpu_feature_shstk (UINT64_C(1) << 24)
57#define cpu_feature_gfni (UINT64_C(1) << 25)
58#define cpu_feature_vaes (UINT64_C(1) << 26)
59#define cpu_feature_avx512bitalg (UINT64_C(1) << 27)
60#define cpu_feature_avx512vpopcntdq (UINT64_C(1) << 28)
61
62// in CPUID Leaf 7, Sub-leaf 0, EDX:
63#define cpu_feature_hybrid (UINT64_C(1) << 29)
64#define cpu_feature_ibt (UINT64_C(1) << 30)
65#define cpu_feature_avx512fp16 (UINT64_C(1) << 31)
66
67// in CPUID Leaf 7, Sub-leaf 1, EAX:
68#define cpu_feature_raoint (UINT64_C(1) << 32)
69#define cpu_feature_cmpccxadd (UINT64_C(1) << 33)
70#define cpu_feature_avxifma (UINT64_C(1) << 34)
71#define cpu_feature_lam (UINT64_C(1) << 35)
72
73// CPU architectures
74#define cpu_x86_64 (0
76#define cpu_core2 (cpu_x86_64
83#define cpu_wsm (cpu_nhm)
84#define cpu_snb (cpu_wsm
86#define cpu_ivb (cpu_snb
94#define cpu_bdw (cpu_hsw)
95#define cpu_bdx (cpu_bdw)
96#define cpu_skl (cpu_bdw)
103#define cpu_clx (cpu_skx)
104#define cpu_cpx (cpu_clx)
114#define cpu_wlc (cpu_snc
117#define cpu_glc (cpu_wlc
119#define cpu_rpc (cpu_glc)
120#define cpu_rwc (cpu_rpc)
121#define cpu_slm (cpu_wsm
123#define cpu_glm (cpu_slm)
124#define cpu_tnt (cpu_glm
136#define cpu_cnl (cpu_plc)
137#define cpu_icl (cpu_snc)
138#define cpu_tgl (cpu_wlc)
139#define cpu_adl (cpu_grt)
140#define cpu_rpl (cpu_grt)
141#define cpu_mtl (cpu_cmt)
142#define cpu_arl (cpu_cmt)
143#define cpu_lnl (cpu_cmt)
144#define cpu_icx (cpu_snc)
145#define cpu_spr (cpu_glc)
146#define cpu_emr (cpu_spr)
147#define cpu_gnr (cpu_glc)
151#define cpu_grr (cpu_srf
153#define cpu_cwf (cpu_srf)
154#define cpu_nehalem (cpu_nhm)
155#define cpu_westmere (cpu_wsm)
156#define cpu_sandybridge (cpu_snb)
157#define cpu_ivybridge (cpu_ivb)
158#define cpu_haswell (cpu_hsw)
159#define cpu_broadwell (cpu_bdw)
160#define cpu_skylake (cpu_skl)
161#define cpu_skylake_avx512 (cpu_skx)
162#define cpu_cascadelake (cpu_clx)
163#define cpu_cooperlake (cpu_cpx)
164#define cpu_palmcove (cpu_plc)
165#define cpu_cannonlake (cpu_cnl)
166#define cpu_sunnycove (cpu_snc)
167#define cpu_icelake_client (cpu_icl)
168#define cpu_icelake_server (cpu_icx)
169#define cpu_willowcove (cpu_wlc)
170#define cpu_tigerlake (cpu_tgl)
171#define cpu_goldencove (cpu_glc)
172#define cpu_alderlake (cpu_adl)
173#define cpu_raptorcove (cpu_rpc)
174#define cpu_raptorlake (cpu_rpl)
175#define cpu_redwoodcove (cpu_rwc)
176#define cpu_meteorlake (cpu_mtl)
177#define cpu_arrowlake (cpu_arl)
178#define cpu_lunarlake (cpu_lnl)
179#define cpu_sapphirerapids (cpu_spr)
180#define cpu_emeraldrapids (cpu_emr)
181#define cpu_graniterapids (cpu_gnr)
182#define cpu_silvermont (cpu_slm)
183#define cpu_goldmont (cpu_glm)
184#define cpu_tremont (cpu_tnt)
185#define cpu_gracemont (cpu_grt)
186#define cpu_crestmont (cpu_cmt)
187#define cpu_grandridge (cpu_grr)
188#define cpu_sierraforest (cpu_srf)
189#define cpu_clearwaterforest (cpu_cwf)
190
191// __attribute__ target strings for GCC and Clang
192#define QT_FUNCTION_TARGET_STRING_SSE2 "sse2"
193#define QT_FUNCTION_TARGET_STRING_SSE3 "sse3"
194#define QT_FUNCTION_TARGET_STRING_SSSE3 "ssse3"
195#define QT_FUNCTION_TARGET_STRING_FMA "fma"
196#define QT_FUNCTION_TARGET_STRING_SSE4_1 "sse4.1"
197#define QT_FUNCTION_TARGET_STRING_SSE4_2 "sse4.2"
198#define QT_FUNCTION_TARGET_STRING_MOVBE "movbe"
199#define QT_FUNCTION_TARGET_STRING_POPCNT "popcnt"
200#define QT_FUNCTION_TARGET_STRING_AES "aes,sse4.2"
201#define QT_FUNCTION_TARGET_STRING_AVX "avx"
202#define QT_FUNCTION_TARGET_STRING_F16C "f16c,avx"
203#define QT_FUNCTION_TARGET_STRING_BMI "bmi"
204#define QT_FUNCTION_TARGET_STRING_AVX2 "avx2,avx"
205#define QT_FUNCTION_TARGET_STRING_BMI2 "bmi2"
206#define QT_FUNCTION_TARGET_STRING_AVX512F "avx512f,avx"
207#define QT_FUNCTION_TARGET_STRING_AVX512DQ "avx512dq,avx512f"
208#define QT_FUNCTION_TARGET_STRING_AVX512IFMA "avx512ifma,avx512f"
209#define QT_FUNCTION_TARGET_STRING_AVX512CD "avx512cd,avx512f"
210#define QT_FUNCTION_TARGET_STRING_SHA "sha"
211#define QT_FUNCTION_TARGET_STRING_AVX512BW "avx512bw,avx512f"
212#define QT_FUNCTION_TARGET_STRING_AVX512VL "avx512vl,avx512f"
213#define QT_FUNCTION_TARGET_STRING_AVX512VBMI "avx512vbmi,avx512f"
214#define QT_FUNCTION_TARGET_STRING_WAITPKG "waitpkg"
215#define QT_FUNCTION_TARGET_STRING_AVX512VBMI2 "avx512vbmi2,avx512f"
216#define QT_FUNCTION_TARGET_STRING_SHSTK "shstk"
217#define QT_FUNCTION_TARGET_STRING_GFNI "gfni"
218#define QT_FUNCTION_TARGET_STRING_VAES "vaes,avx2,avx,aes"
219#define QT_FUNCTION_TARGET_STRING_AVX512BITALG "avx512bitalg,avx512f"
220#define QT_FUNCTION_TARGET_STRING_AVX512VPOPCNTDQ "avx512vpopcntdq,avx512f"
221#define QT_FUNCTION_TARGET_STRING_HYBRID "hybrid"
222#define QT_FUNCTION_TARGET_STRING_IBT "ibt"
223#define QT_FUNCTION_TARGET_STRING_AVX512FP16 "avx512fp16,avx512f,f16c"
224#define QT_FUNCTION_TARGET_STRING_RAOINT "raoint"
225#define QT_FUNCTION_TARGET_STRING_CMPCCXADD "cmpccxadd"
226#define QT_FUNCTION_TARGET_STRING_AVXIFMA "avxifma,avx"
227#define QT_FUNCTION_TARGET_STRING_LAM "lam"
228#define QT_FUNCTION_TARGET_STRING_ARCH_X86_64 "sse2"
229#define QT_FUNCTION_TARGET_STRING_ARCH_CORE2 QT_FUNCTION_TARGET_STRING_ARCH_X86_64 ",sse3,ssse3,cx16"
230#define QT_FUNCTION_TARGET_STRING_ARCH_NHM QT_FUNCTION_TARGET_STRING_ARCH_CORE2 ",sse4.1,sse4.2,popcnt"
231#define QT_FUNCTION_TARGET_STRING_ARCH_WSM QT_FUNCTION_TARGET_STRING_ARCH_NHM
232#define QT_FUNCTION_TARGET_STRING_ARCH_SNB QT_FUNCTION_TARGET_STRING_ARCH_WSM ",avx"
233#define QT_FUNCTION_TARGET_STRING_ARCH_IVB QT_FUNCTION_TARGET_STRING_ARCH_SNB ",f16c,fsgsbase"
234#define QT_FUNCTION_TARGET_STRING_ARCH_HSW QT_FUNCTION_TARGET_STRING_ARCH_IVB ",avx2,fma,bmi,bmi2,lzcnt,movbe"
235#define QT_FUNCTION_TARGET_STRING_ARCH_BDW QT_FUNCTION_TARGET_STRING_ARCH_HSW ",adx"
236#define QT_FUNCTION_TARGET_STRING_ARCH_BDX QT_FUNCTION_TARGET_STRING_ARCH_BDW
237#define QT_FUNCTION_TARGET_STRING_ARCH_SKL QT_FUNCTION_TARGET_STRING_ARCH_BDW ",xsavec,xsaves"
238#define QT_FUNCTION_TARGET_STRING_ARCH_SKX QT_FUNCTION_TARGET_STRING_ARCH_SKL ",avx512f,avx512dq,avx512cd,avx512bw,avx512vl"
239#define QT_FUNCTION_TARGET_STRING_ARCH_CLX QT_FUNCTION_TARGET_STRING_ARCH_SKX ",avx512vnni"
240#define QT_FUNCTION_TARGET_STRING_ARCH_CPX QT_FUNCTION_TARGET_STRING_ARCH_CLX ",avx512bf16"
241#define QT_FUNCTION_TARGET_STRING_ARCH_PLC QT_FUNCTION_TARGET_STRING_ARCH_SKX ",avx512ifma,avx512vbmi"
242#define QT_FUNCTION_TARGET_STRING_ARCH_SNC QT_FUNCTION_TARGET_STRING_ARCH_PLC ",avx512vbmi2,gfni,vaes,vpclmulqdq,avx512vnni,avx512bitalg,avx512vpopcntdq"
243#define QT_FUNCTION_TARGET_STRING_ARCH_WLC QT_FUNCTION_TARGET_STRING_ARCH_SNC ",shstk,movdiri,movdir64b,ibt,keylocker"
244#define QT_FUNCTION_TARGET_STRING_ARCH_GLC QT_FUNCTION_TARGET_STRING_ARCH_WLC ",avx512bf16,avxvnni,cldemote,waitpkg,serialize,uintr"
245#define QT_FUNCTION_TARGET_STRING_ARCH_RPC QT_FUNCTION_TARGET_STRING_ARCH_GLC
246#define QT_FUNCTION_TARGET_STRING_ARCH_RWC QT_FUNCTION_TARGET_STRING_ARCH_RPC ",prefetchiti"
247#define QT_FUNCTION_TARGET_STRING_ARCH_SLM QT_FUNCTION_TARGET_STRING_ARCH_WSM ",rdrnd,movbe"
248#define QT_FUNCTION_TARGET_STRING_ARCH_GLM QT_FUNCTION_TARGET_STRING_ARCH_SLM ",fsgsbase,rdseed,lzcnt,xsavec,xsaves"
249#define QT_FUNCTION_TARGET_STRING_ARCH_TNT QT_FUNCTION_TARGET_STRING_ARCH_GLM ",clwb,gfni,cldemote,waitpkg,movdiri,movdir64b"
250#define QT_FUNCTION_TARGET_STRING_ARCH_GRT QT_FUNCTION_TARGET_STRING_ARCH_SKL ",avxvnni,gfni,vaes,vpclmulqdq,serialize,shstk,cldemote,movdiri,movdir64b,ibt,waitpkg,keylocker"
251#define QT_FUNCTION_TARGET_STRING_ARCH_CMT QT_FUNCTION_TARGET_STRING_ARCH_GRT ",cmpccxadd,avxifma,avxneconvert,avxvnniint8"
252#define QT_FUNCTION_TARGET_STRING_ARCH_CNL QT_FUNCTION_TARGET_STRING_ARCH_PLC
253#define QT_FUNCTION_TARGET_STRING_ARCH_ICL QT_FUNCTION_TARGET_STRING_ARCH_SNC
254#define QT_FUNCTION_TARGET_STRING_ARCH_TGL QT_FUNCTION_TARGET_STRING_ARCH_WLC
255#define QT_FUNCTION_TARGET_STRING_ARCH_ADL QT_FUNCTION_TARGET_STRING_ARCH_GRT
256#define QT_FUNCTION_TARGET_STRING_ARCH_RPL QT_FUNCTION_TARGET_STRING_ARCH_GRT
257#define QT_FUNCTION_TARGET_STRING_ARCH_MTL QT_FUNCTION_TARGET_STRING_ARCH_CMT
258#define QT_FUNCTION_TARGET_STRING_ARCH_ARL QT_FUNCTION_TARGET_STRING_ARCH_CMT
259#define QT_FUNCTION_TARGET_STRING_ARCH_LNL QT_FUNCTION_TARGET_STRING_ARCH_CMT
260#define QT_FUNCTION_TARGET_STRING_ARCH_ICX QT_FUNCTION_TARGET_STRING_ARCH_SNC ",pconfig"
261#define QT_FUNCTION_TARGET_STRING_ARCH_SPR QT_FUNCTION_TARGET_STRING_ARCH_GLC ",pconfig,amx-tile,amx-bf16,amx-int8"
262#define QT_FUNCTION_TARGET_STRING_ARCH_EMR QT_FUNCTION_TARGET_STRING_ARCH_SPR
263#define QT_FUNCTION_TARGET_STRING_ARCH_GNR QT_FUNCTION_TARGET_STRING_ARCH_GLC ",pconfig,amx-tile,amx-bf16,amx-int8,amx-fp16,amx-complex"
264#define QT_FUNCTION_TARGET_STRING_ARCH_SRF QT_FUNCTION_TARGET_STRING_ARCH_CMT ",cmpccxadd,avxifma,avxneconvert,avxvnniint8"
265#define QT_FUNCTION_TARGET_STRING_ARCH_GRR QT_FUNCTION_TARGET_STRING_ARCH_SRF ",raoint"
266#define QT_FUNCTION_TARGET_STRING_ARCH_CWF QT_FUNCTION_TARGET_STRING_ARCH_SRF
267#define QT_FUNCTION_TARGET_STRING_ARCH_NEHALEM QT_FUNCTION_TARGET_STRING_ARCH_NHM
268#define QT_FUNCTION_TARGET_STRING_ARCH_WESTMERE QT_FUNCTION_TARGET_STRING_ARCH_WSM
269#define QT_FUNCTION_TARGET_STRING_ARCH_SANDYBRIDGE QT_FUNCTION_TARGET_STRING_ARCH_SNB
270#define QT_FUNCTION_TARGET_STRING_ARCH_IVYBRIDGE QT_FUNCTION_TARGET_STRING_ARCH_IVB
271#define QT_FUNCTION_TARGET_STRING_ARCH_HASWELL QT_FUNCTION_TARGET_STRING_ARCH_HSW
272#define QT_FUNCTION_TARGET_STRING_ARCH_BROADWELL QT_FUNCTION_TARGET_STRING_ARCH_BDW
273#define QT_FUNCTION_TARGET_STRING_ARCH_SKYLAKE QT_FUNCTION_TARGET_STRING_ARCH_SKL
274#define QT_FUNCTION_TARGET_STRING_ARCH_SKYLAKE_AVX512 QT_FUNCTION_TARGET_STRING_ARCH_SKX
275#define QT_FUNCTION_TARGET_STRING_ARCH_CASCADELAKE QT_FUNCTION_TARGET_STRING_ARCH_CLX
276#define QT_FUNCTION_TARGET_STRING_ARCH_COOPERLAKE QT_FUNCTION_TARGET_STRING_ARCH_CPX
277#define QT_FUNCTION_TARGET_STRING_ARCH_PALMCOVE QT_FUNCTION_TARGET_STRING_ARCH_PLC
278#define QT_FUNCTION_TARGET_STRING_ARCH_CANNONLAKE QT_FUNCTION_TARGET_STRING_ARCH_CNL
279#define QT_FUNCTION_TARGET_STRING_ARCH_SUNNYCOVE QT_FUNCTION_TARGET_STRING_ARCH_SNC
280#define QT_FUNCTION_TARGET_STRING_ARCH_ICELAKE_CLIENT QT_FUNCTION_TARGET_STRING_ARCH_ICL
281#define QT_FUNCTION_TARGET_STRING_ARCH_ICELAKE_SERVER QT_FUNCTION_TARGET_STRING_ARCH_ICX
282#define QT_FUNCTION_TARGET_STRING_ARCH_WILLOWCOVE QT_FUNCTION_TARGET_STRING_ARCH_WLC
283#define QT_FUNCTION_TARGET_STRING_ARCH_TIGERLAKE QT_FUNCTION_TARGET_STRING_ARCH_TGL
284#define QT_FUNCTION_TARGET_STRING_ARCH_GOLDENCOVE QT_FUNCTION_TARGET_STRING_ARCH_GLC
285#define QT_FUNCTION_TARGET_STRING_ARCH_ALDERLAKE QT_FUNCTION_TARGET_STRING_ARCH_ADL
286#define QT_FUNCTION_TARGET_STRING_ARCH_RAPTORCOVE QT_FUNCTION_TARGET_STRING_ARCH_RPC
287#define QT_FUNCTION_TARGET_STRING_ARCH_RAPTORLAKE QT_FUNCTION_TARGET_STRING_ARCH_RPL
288#define QT_FUNCTION_TARGET_STRING_ARCH_REDWOODCOVE QT_FUNCTION_TARGET_STRING_ARCH_RWC
289#define QT_FUNCTION_TARGET_STRING_ARCH_METEORLAKE QT_FUNCTION_TARGET_STRING_ARCH_MTL
290#define QT_FUNCTION_TARGET_STRING_ARCH_ARROWLAKE QT_FUNCTION_TARGET_STRING_ARCH_ARL
291#define QT_FUNCTION_TARGET_STRING_ARCH_LUNARLAKE QT_FUNCTION_TARGET_STRING_ARCH_LNL
292#define QT_FUNCTION_TARGET_STRING_ARCH_SAPPHIRERAPIDS QT_FUNCTION_TARGET_STRING_ARCH_SPR
293#define QT_FUNCTION_TARGET_STRING_ARCH_EMERALDRAPIDS QT_FUNCTION_TARGET_STRING_ARCH_EMR
294#define QT_FUNCTION_TARGET_STRING_ARCH_GRANITERAPIDS QT_FUNCTION_TARGET_STRING_ARCH_GNR
295#define QT_FUNCTION_TARGET_STRING_ARCH_SILVERMONT QT_FUNCTION_TARGET_STRING_ARCH_SLM
296#define QT_FUNCTION_TARGET_STRING_ARCH_GOLDMONT QT_FUNCTION_TARGET_STRING_ARCH_GLM
297#define QT_FUNCTION_TARGET_STRING_ARCH_TREMONT QT_FUNCTION_TARGET_STRING_ARCH_TNT
298#define QT_FUNCTION_TARGET_STRING_ARCH_GRACEMONT QT_FUNCTION_TARGET_STRING_ARCH_GRT
299#define QT_FUNCTION_TARGET_STRING_ARCH_CRESTMONT QT_FUNCTION_TARGET_STRING_ARCH_CMT
300#define QT_FUNCTION_TARGET_STRING_ARCH_GRANDRIDGE QT_FUNCTION_TARGET_STRING_ARCH_GRR
301#define QT_FUNCTION_TARGET_STRING_ARCH_SIERRAFOREST QT_FUNCTION_TARGET_STRING_ARCH_SRF
302#define QT_FUNCTION_TARGET_STRING_ARCH_CLEARWATERFOREST QT_FUNCTION_TARGET_STRING_ARCH_CWF
303
304static const uint64_t _compilerCpuFeatures = 0
305#ifdef __SSE2__
307#endif
308#ifdef __SSE3__
309 | cpu_feature_sse3
310#endif
311#ifdef __SSSE3__
312 | cpu_feature_ssse3
313#endif
314#ifdef __FMA__
315 | cpu_feature_fma
316#endif
317#ifdef __SSE4_1__
318 | cpu_feature_sse4_1
319#endif
320#ifdef __SSE4_2__
321 | cpu_feature_sse4_2
322#endif
323#ifdef __MOVBE__
324 | cpu_feature_movbe
325#endif
326#ifdef __POPCNT__
327 | cpu_feature_popcnt
328#endif
329#ifdef __AES__
330 | cpu_feature_aes
331#endif
332#ifdef __AVX__
333 | cpu_feature_avx
334#endif
335#ifdef __F16C__
336 | cpu_feature_f16c
337#endif
338#ifdef __BMI__
339 | cpu_feature_bmi
340#endif
341#ifdef __AVX2__
342 | cpu_feature_avx2
343#endif
344#ifdef __BMI2__
345 | cpu_feature_bmi2
346#endif
347#ifdef __AVX512F__
348 | cpu_feature_avx512f
349#endif
350#ifdef __AVX512DQ__
351 | cpu_feature_avx512dq
352#endif
353#ifdef __AVX512IFMA__
354 | cpu_feature_avx512ifma
355#endif
356#ifdef __AVX512CD__
357 | cpu_feature_avx512cd
358#endif
359#ifdef __SHA__
360 | cpu_feature_sha
361#endif
362#ifdef __AVX512BW__
363 | cpu_feature_avx512bw
364#endif
365#ifdef __AVX512VL__
366 | cpu_feature_avx512vl
367#endif
368#ifdef __AVX512VBMI__
369 | cpu_feature_avx512vbmi
370#endif
371#ifdef __WAITPKG__
372 | cpu_feature_waitpkg
373#endif
374#ifdef __AVX512VBMI2__
375 | cpu_feature_avx512vbmi2
376#endif
377#ifdef __SHSTK__
378 | cpu_feature_shstk
379#endif
380#ifdef __GFNI__
381 | cpu_feature_gfni
382#endif
383#ifdef __VAES__
384 | cpu_feature_vaes
385#endif
386#ifdef __AVX512BITALG__
387 | cpu_feature_avx512bitalg
388#endif
389#ifdef __AVX512VPOPCNTDQ__
390 | cpu_feature_avx512vpopcntdq
391#endif
392#ifdef __HYBRID__
393 | cpu_feature_hybrid
394#endif
395#ifdef __IBT__
396 | cpu_feature_ibt
397#endif
398#ifdef __AVX512FP16__
399 | cpu_feature_avx512fp16
400#endif
401#ifdef __RAOINT__
402 | cpu_feature_raoint
403#endif
404#ifdef __CMPCCXADD__
405 | cpu_feature_cmpccxadd
406#endif
407#ifdef __AVXIFMA__
408 | cpu_feature_avxifma
409#endif
410#ifdef __LAM__
411 | cpu_feature_lam
412#endif
413 ;
414
415#if (defined __cplusplus) && __cplusplus >= 201103L
416enum X86CpuFeatures : uint64_t {
417 CpuFeatureSSE2 = cpu_feature_sse2, ///< Streaming SIMD Extensions 2
418 CpuFeatureSSE3 = cpu_feature_sse3, ///< Streaming SIMD Extensions 3
419 CpuFeatureSSSE3 = cpu_feature_ssse3, ///< Supplemental Streaming SIMD Extensions 3
420 CpuFeatureFMA = cpu_feature_fma, ///< Fused Multiply-Add
421 CpuFeatureSSE4_1 = cpu_feature_sse4_1, ///< Streaming SIMD Extensions 4.1
422 CpuFeatureSSE4_2 = cpu_feature_sse4_2, ///< Streaming SIMD Extensions 4.2
423 CpuFeatureMOVBE = cpu_feature_movbe, ///< MOV Big Endian
424 CpuFeaturePOPCNT = cpu_feature_popcnt, ///< Population count
425 CpuFeatureAES = cpu_feature_aes, ///< Advenced Encryption Standard
426 CpuFeatureAVX = cpu_feature_avx, ///< Advanced Vector Extensions
427 CpuFeatureF16C = cpu_feature_f16c, ///< 16-bit Float Conversion
428 CpuFeatureBMI = cpu_feature_bmi, ///< Bit Manipulation Instructions
429 CpuFeatureAVX2 = cpu_feature_avx2, ///< Advanced Vector Extensions 2
430 CpuFeatureBMI2 = cpu_feature_bmi2, ///< Bit Manipulation Instructions 2
431 CpuFeatureAVX512F = cpu_feature_avx512f, ///< AVX512 Foundation
432 CpuFeatureAVX512DQ = cpu_feature_avx512dq, ///< AVX512 Double & Quadword
433 CpuFeatureAVX512IFMA = cpu_feature_avx512ifma, ///< AVX512 Integer Fused Multiply-Add
434 CpuFeatureAVX512CD = cpu_feature_avx512cd, ///< AVX512 Conflict Detection
435 CpuFeatureSHA = cpu_feature_sha, ///< SHA-1 and SHA-256 instructions
436 CpuFeatureAVX512BW = cpu_feature_avx512bw, ///< AVX512 Byte & Word
437 CpuFeatureAVX512VL = cpu_feature_avx512vl, ///< AVX512 Vector Length
438 CpuFeatureAVX512VBMI = cpu_feature_avx512vbmi, ///< AVX512 Vector Byte Manipulation Instructions
439 CpuFeatureWAITPKG = cpu_feature_waitpkg, ///< User-Level Monitor / Wait
440 CpuFeatureAVX512VBMI2 = cpu_feature_avx512vbmi2, ///< AVX512 Vector Byte Manipulation Instructions 2
441 CpuFeatureSHSTK = cpu_feature_shstk, ///< Control Flow Enforcement Technology Shadow Stack
442 CpuFeatureGFNI = cpu_feature_gfni, ///< Galois Field new instructions
443 CpuFeatureVAES = cpu_feature_vaes, ///< 256- and 512-bit AES
444 CpuFeatureAVX512BITALG = cpu_feature_avx512bitalg, ///< AVX512 Bit Algorithms
445 CpuFeatureAVX512VPOPCNTDQ = cpu_feature_avx512vpopcntdq, ///< AVX512 Population Count
446 CpuFeatureHYBRID = cpu_feature_hybrid, ///< Hybrid processor
447 CpuFeatureIBT = cpu_feature_ibt, ///< Control Flow Enforcement Technology Indirect Branch Tracking
448 CpuFeatureAVX512FP16 = cpu_feature_avx512fp16, ///< AVX512 16-bit Floating Point
449 CpuFeatureRAOINT = cpu_feature_raoint, ///< Remote Atomic Operations, Integer
450 CpuFeatureCMPCCXADD = cpu_feature_cmpccxadd, ///< CMPccXADD instructions
451 CpuFeatureAVXIFMA = cpu_feature_avxifma, ///< AVX-IFMA instructions
452 CpuFeatureLAM = cpu_feature_lam, ///< Linear Address Masking
453}; // enum X86CpuFeatures
454
455enum X86CpuArchitectures : uint64_t {
456 CpuArchx8664 = cpu_x86_64,
457 CpuArchCore2 = cpu_core2,
458 CpuArchNHM = cpu_nhm,
459 CpuArchWSM = cpu_wsm,
460 CpuArchSNB = cpu_snb,
461 CpuArchIVB = cpu_ivb, ///< rdrnd
462 CpuArchHSW = cpu_hsw, ///< hle,rtm
463 CpuArchBDW = cpu_bdw, ///< rdseed
464 CpuArchBDX = cpu_bdx,
465 CpuArchSKL = cpu_skl,
466 CpuArchSKX = cpu_skx, ///< clwb
467 CpuArchCLX = cpu_clx,
468 CpuArchCPX = cpu_cpx,
469 CpuArchPLC = cpu_plc, ///< sha
470 CpuArchSNC = cpu_snc, ///< fsrm,rdpid
471 CpuArchWLC = cpu_wlc, ///< avx512vp2intersect
472 CpuArchGLC = cpu_glc, ///< tsxldtrk
473 CpuArchRPC = cpu_rpc,
474 CpuArchRWC = cpu_rwc,
475 CpuArchSLM = cpu_slm,
476 CpuArchGLM = cpu_glm,
477 CpuArchTNT = cpu_tnt,
478 CpuArchGRT = cpu_grt, ///< rdpid
479 CpuArchCMT = cpu_cmt,
480 CpuArchCNL = cpu_cnl,
481 CpuArchICL = cpu_icl,
482 CpuArchTGL = cpu_tgl,
483 CpuArchADL = cpu_adl,
484 CpuArchRPL = cpu_rpl,
485 CpuArchMTL = cpu_mtl,
486 CpuArchARL = cpu_arl,
487 CpuArchLNL = cpu_lnl,
488 CpuArchICX = cpu_icx,
489 CpuArchSPR = cpu_spr,
490 CpuArchEMR = cpu_emr,
491 CpuArchGNR = cpu_gnr,
492 CpuArchSRF = cpu_srf,
493 CpuArchGRR = cpu_grr,
494 CpuArchCWF = cpu_cwf,
495 CpuArchNehalem = cpu_nehalem, ///< Intel Core i3/i5/i7
496 CpuArchWestmere = cpu_westmere, ///< Intel Core i3/i5/i7
497 CpuArchSandyBridge = cpu_sandybridge, ///< Second Generation Intel Core i3/i5/i7
498 CpuArchIvyBridge = cpu_ivybridge, ///< Third Generation Intel Core i3/i5/i7
499 CpuArchHaswell = cpu_haswell, ///< Fourth Generation Intel Core i3/i5/i7
500 CpuArchBroadwell = cpu_broadwell, ///< Fifth Generation Intel Core i3/i5/i7
501 CpuArchSkylake = cpu_skylake, ///< Sixth Generation Intel Core i3/i5/i7
502 CpuArchSkylakeAvx512 = cpu_skylake_avx512, ///< Intel Xeon Scalable
503 CpuArchCascadeLake = cpu_cascadelake, ///< Second Generation Intel Xeon Scalable
504 CpuArchCooperLake = cpu_cooperlake, ///< Third Generation Intel Xeon Scalable
505 CpuArchPalmCove = cpu_palmcove,
506 CpuArchCannonLake = cpu_cannonlake, ///< Intel Core i3-8121U
507 CpuArchSunnyCove = cpu_sunnycove,
508 CpuArchIceLakeClient = cpu_icelake_client, ///< Tenth Generation Intel Core i3/i5/i7
509 CpuArchIceLakeServer = cpu_icelake_server, ///< Third Generation Intel Xeon Scalable
510 CpuArchWillowCove = cpu_willowcove,
511 CpuArchTigerLake = cpu_tigerlake, ///< Eleventh Generation Intel Core i3/i5/i7
512 CpuArchGoldenCove = cpu_goldencove,
513 CpuArchAlderLake = cpu_alderlake, ///< Twelfth Generation Intel Core
514 CpuArchRaptorCove = cpu_raptorcove,
515 CpuArchRaptorLake = cpu_raptorlake, ///< Thirteenth Generation Intel Core
516 CpuArchRedwoodCove = cpu_redwoodcove,
517 CpuArchMeteorLake = cpu_meteorlake,
518 CpuArchArrowLake = cpu_arrowlake,
519 CpuArchLunarLake = cpu_lunarlake,
520 CpuArchSapphireRapids = cpu_sapphirerapids, ///< Fourth Generation Intel Xeon Scalable
521 CpuArchEmeraldRapids = cpu_emeraldrapids, ///< Fifth Generation Intel Xeon Scalable
522 CpuArchGraniteRapids = cpu_graniterapids,
523 CpuArchSilvermont = cpu_silvermont,
524 CpuArchGoldmont = cpu_goldmont,
525 CpuArchTremont = cpu_tremont,
526 CpuArchGracemont = cpu_gracemont,
527 CpuArchCrestmont = cpu_crestmont,
528 CpuArchGrandRidge = cpu_grandridge,
529 CpuArchSierraForest = cpu_sierraforest,
530 CpuArchClearwaterForest = cpu_clearwaterforest,
531}; // enum X86cpuArchitectures
532#endif /* C++11 */
533
534#endif /* QSIMD_X86_P_H */
XSaveBits
@ XSave_Bndcsr
@ XSave_X87
@ XSave_HwpState
@ XSave_AvxState
@ XSave_Xtilecfg
@ XSave_Xtiledata
@ XSave_Avx512State
@ XSave_AmxState
@ XSave_SseState
@ XSave_HdcState
@ XSave_PKRUState
@ XSave_OpMask
@ XSave_CetUState
@ XSave_Zmm_Hi256
@ XSave_CetState
@ XSave_Bndregs
@ XSave_UintrState
@ XSave_PTState
@ XSave_Ymm_Hi128
@ XSave_CetSState
@ XSave_Hi16_Zmm
@ XSave_MPXState
static const struct X86Architecture x86_architectures[]
X86CpuidLeaves
Definition qsimd_x86.cpp:56
@ Leaf01EDX
Definition qsimd_x86.cpp:57
@ Leaf07_01EAX
Definition qsimd_x86.cpp:62
@ Leaf07_00ECX
Definition qsimd_x86.cpp:60
@ Leaf80000008hEBX
Definition qsimd_x86.cpp:66
@ Leaf07_00EBX
Definition qsimd_x86.cpp:59
@ Leaf07_00EDX
Definition qsimd_x86.cpp:61
@ Leaf13_01EAX
Definition qsimd_x86.cpp:64
@ X86CpuidMaxLeaf
Definition qsimd_x86.cpp:67
@ Leaf07_01EDX
Definition qsimd_x86.cpp:63
@ Leaf01ECX
Definition qsimd_x86.cpp:58
@ Leaf80000001hECX
Definition qsimd_x86.cpp:65
static const uint16_t x86_locators[]
Definition qsimd_x86.cpp:70
static const uint64_t XSaveReq_AvxState
static const uint16_t features_indices[]
Definition qsimd_x86.cpp:48
static const char features_string[]
Definition qsimd_x86.cpp:9
static const uint64_t XSaveReq_CetState
static const struct XSaveRequirementMapping xsave_requirements[]
static const uint64_t XSaveReq_Avx512State
#define cpu_skx
Definition qsimd_x86_p.h:97
#define cpu_lunarlake
#define cpu_raptorlake
#define QT_FUNCTION_TARGET_STRING_ARCH_LNL
#define cpu_feature_gfni
Definition qsimd_x86_p.h:57
#define cpu_spr
#define cpu_rpl
#define cpu_haswell
#define QT_FUNCTION_TARGET_STRING_ARCH_ICL
#define cpu_feature_bmi2
Definition qsimd_x86_p.h:43
#define cpu_feature_bmi
Definition qsimd_x86_p.h:41
#define QT_FUNCTION_TARGET_STRING_ARCH_CORE2
static const uint64_t _compilerCpuFeatures
#define cpu_feature_waitpkg
Definition qsimd_x86_p.h:54
#define cpu_cwf
#define cpu_feature_avx
Definition qsimd_x86_p.h:37
#define cpu_sierraforest
#define cpu_westmere
#define cpu_redwoodcove
#define QT_FUNCTION_TARGET_STRING_ARCH_IVB
#define QT_FUNCTION_TARGET_STRING_ARCH_HSW
#define cpu_alderlake
#define QT_FUNCTION_TARGET_STRING_ARCH_EMR
#define cpu_rpc
#define cpu_feature_fma
Definition qsimd_x86_p.h:31
#define QT_FUNCTION_TARGET_STRING_ARCH_CLX
#define cpu_skylake
#define cpu_feature_sse4_2
Definition qsimd_x86_p.h:33
#define cpu_feature_shstk
Definition qsimd_x86_p.h:56
#define QT_FUNCTION_TARGET_STRING_ARCH_ICX
#define cpu_srf
#define cpu_tgl
#define cpu_feature_ssse3
Definition qsimd_x86_p.h:30
#define cpu_icelake_server
#define cpu_skl
Definition qsimd_x86_p.h:96
#define cpu_arl
#define cpu_meteorlake
#define cpu_feature_avx512ifma
Definition qsimd_x86_p.h:46
#define cpu_gracemont
#define cpu_feature_avx512vpopcntdq
Definition qsimd_x86_p.h:60
#define cpu_graniterapids
#define cpu_feature_avx512f
Definition qsimd_x86_p.h:44
#define cpu_snb
Definition qsimd_x86_p.h:84
#define cpu_feature_sha
Definition qsimd_x86_p.h:48
#define cpu_clearwaterforest
#define cpu_icelake_client
#define cpu_cannonlake
#define cpu_gnr
#define cpu_willowcove
#define cpu_feature_avx2
Definition qsimd_x86_p.h:42
#define cpu_cmt
#define QT_FUNCTION_TARGET_STRING_ARCH_WSM
#define cpu_feature_aes
Definition qsimd_x86_p.h:36
#define cpu_bdw
Definition qsimd_x86_p.h:94
#define cpu_grr
#define cpu_feature_vaes
Definition qsimd_x86_p.h:58
#define cpu_core2
Definition qsimd_x86_p.h:76
#define cpu_feature_avx512vl
Definition qsimd_x86_p.h:50
#define QT_FUNCTION_TARGET_STRING_ARCH_GLM
#define QT_FUNCTION_TARGET_STRING_ARCH_MTL
#define cpu_slm
#define cpu_wlc
#define cpu_feature_cmpccxadd
Definition qsimd_x86_p.h:69
#define cpu_feature_lam
Definition qsimd_x86_p.h:71
#define cpu_cooperlake
#define QT_FUNCTION_TARGET_STRING_ARCH_X86_64
#define cpu_feature_sse3
Definition qsimd_x86_p.h:29
#define cpu_sunnycove
#define cpu_x86_64
Definition qsimd_x86_p.h:74
#define cpu_feature_avx512bitalg
Definition qsimd_x86_p.h:59
#define cpu_feature_sse2
Definition qsimd_x86_p.h:26
#define cpu_ivybridge
#define QT_FUNCTION_TARGET_STRING_ARCH_TNT
#define cpu_wsm
Definition qsimd_x86_p.h:83
#define cpu_feature_avx512dq
Definition qsimd_x86_p.h:45
#define cpu_lnl
#define QT_FUNCTION_TARGET_STRING_ARCH_RWC
#define QT_FUNCTION_TARGET_STRING_ARCH_CWF
#define cpu_grandridge
#define cpu_rwc
#define cpu_snc
#define QT_FUNCTION_TARGET_STRING_ARCH_GLC
#define QT_FUNCTION_TARGET_STRING_ARCH_CNL
#define QT_FUNCTION_TARGET_STRING_ARCH_CMT
#define cpu_icl
#define cpu_emeraldrapids
#define cpu_glm
#define cpu_cpx
#define QT_FUNCTION_TARGET_STRING_ARCH_PLC
#define QT_FUNCTION_TARGET_STRING_ARCH_GNR
#define cpu_grt
#define cpu_plc
#define cpu_feature_raoint
Definition qsimd_x86_p.h:68
#define QT_FUNCTION_TARGET_STRING_ARCH_WLC
#define cpu_tigerlake
#define cpu_clx
#define QT_FUNCTION_TARGET_STRING_ARCH_ARL
#define cpu_cascadelake
#define QT_FUNCTION_TARGET_STRING_ARCH_SNC
#define cpu_tnt
#define QT_FUNCTION_TARGET_STRING_ARCH_BDW
#define cpu_tremont
#define QT_FUNCTION_TARGET_STRING_ARCH_RPL
#define cpu_glc
#define cpu_nhm
Definition qsimd_x86_p.h:79
#define QT_FUNCTION_TARGET_STRING_ARCH_SLM
#define cpu_feature_ibt
Definition qsimd_x86_p.h:64
#define cpu_feature_f16c
Definition qsimd_x86_p.h:38
#define QT_FUNCTION_TARGET_STRING_ARCH_GRR
#define QT_FUNCTION_TARGET_STRING_ARCH_GRT
#define QT_FUNCTION_TARGET_STRING_ARCH_SKX
#define cpu_goldencove
#define cpu_feature_avx512vbmi2
Definition qsimd_x86_p.h:55
#define cpu_skylake_avx512
#define cpu_feature_avx512fp16
Definition qsimd_x86_p.h:65
#define QT_FUNCTION_TARGET_STRING_ARCH_RPC
#define cpu_nehalem
#define cpu_feature_avxifma
Definition qsimd_x86_p.h:70
#define QT_FUNCTION_TARGET_STRING_ARCH_SRF
#define cpu_emr
#define cpu_icx
#define cpu_adl
#define cpu_cnl
#define cpu_feature_avx512bw
Definition qsimd_x86_p.h:49
#define cpu_palmcove
#define cpu_bdx
Definition qsimd_x86_p.h:95
#define QT_FUNCTION_TARGET_STRING_ARCH_SKL
#define QT_FUNCTION_TARGET_STRING_ARCH_CPX
#define cpu_feature_sse4_1
Definition qsimd_x86_p.h:32
#define QT_FUNCTION_TARGET_STRING_ARCH_SPR
#define QT_FUNCTION_TARGET_STRING_ARCH_TGL
#define cpu_feature_hybrid
Definition qsimd_x86_p.h:63
#define cpu_sandybridge
#define cpu_crestmont
#define cpu_goldmont
#define cpu_arrowlake
#define cpu_silvermont
#define QT_FUNCTION_TARGET_STRING_ARCH_SNB
#define cpu_broadwell
#define cpu_feature_popcnt
Definition qsimd_x86_p.h:35
#define cpu_mtl
#define cpu_hsw
Definition qsimd_x86_p.h:88
#define cpu_feature_movbe
Definition qsimd_x86_p.h:34
#define QT_FUNCTION_TARGET_STRING_ARCH_ADL
#define cpu_raptorcove
#define QT_FUNCTION_TARGET_STRING_ARCH_NHM
#define cpu_ivb
Definition qsimd_x86_p.h:86
#define cpu_feature_avx512vbmi
Definition qsimd_x86_p.h:53
#define cpu_feature_avx512cd
Definition qsimd_x86_p.h:47
#define cpu_sapphirerapids
uint64_t features
char name[17+1]