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qsimd_x86.cpp
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1
// Copyright (C) 2022 Intel Corporation.
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// SPDX-License-Identifier: LicenseRef-Qt-Commercial OR LGPL-3.0-only OR GPL-2.0-only OR GPL-3.0-only
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// This is a generated file. DO NOT EDIT.
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// Please see util/x86simdgen/README.md
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#include "
qsimd_x86_p.h
"
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static
const
char
features_string
[] =
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" sse2\0"
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" sse3\0"
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" ssse3\0"
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" fma\0"
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" sse4.1\0"
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" sse4.2\0"
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" movbe\0"
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" popcnt\0"
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" aes\0"
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" avx\0"
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" f16c\0"
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" rdrnd\0"
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" bmi\0"
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" avx2\0"
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" bmi2\0"
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" avx512f\0"
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" avx512dq\0"
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" rdseed\0"
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" avx512ifma\0"
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" avx512cd\0"
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" sha\0"
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" avx512bw\0"
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" avx512vl\0"
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" avx512vbmi\0"
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" waitpkg\0"
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" avx512vbmi2\0"
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" shstk\0"
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" gfni\0"
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" vaes\0"
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" avx512bitalg\0"
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" avx512vpopcntdq\0"
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" hybrid\0"
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" ibt\0"
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" avx512fp16\0"
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" raoint\0"
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" cmpccxadd\0"
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" avxifma\0"
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" lam\0"
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"\0"
;
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static
const
uint16_t
features_indices
[] = {
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0, 6, 12, 19, 24, 32, 40, 47,
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55, 60, 65, 71, 78, 83, 89, 95,
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104, 114, 122, 134, 144, 149, 159, 169,
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181, 190, 203, 210, 216, 222, 236, 253,
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261, 266, 278, 286, 297, 306,
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};
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enum
X86CpuidLeaves
{
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Leaf01EDX
,
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Leaf01ECX
,
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Leaf07_00EBX
,
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Leaf07_00ECX
,
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Leaf07_00EDX
,
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Leaf07_01EAX
,
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Leaf07_01EDX
,
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Leaf13_01EAX
,
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Leaf80000001hECX
,
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Leaf80000008hEBX
,
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X86CpuidMaxLeaf
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};
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static
const
uint16_t
x86_locators
[] = {
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Leaf01EDX
*32 + 26,
// sse2
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Leaf01ECX
*32 + 0,
// sse3
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Leaf01ECX
*32 + 9,
// ssse3
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Leaf01ECX
*32 + 12,
// fma
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Leaf01ECX
*32 + 19,
// sse4.1
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Leaf01ECX
*32 + 20,
// sse4.2
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Leaf01ECX
*32 + 22,
// movbe
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Leaf01ECX
*32 + 23,
// popcnt
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Leaf01ECX
*32 + 25,
// aes
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Leaf01ECX
*32 + 28,
// avx
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Leaf01ECX
*32 + 29,
// f16c
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Leaf01ECX
*32 + 30,
// rdrnd
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Leaf07_00EBX
*32 + 3,
// bmi
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Leaf07_00EBX
*32 + 5,
// avx2
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Leaf07_00EBX
*32 + 8,
// bmi2
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Leaf07_00EBX
*32 + 16,
// avx512f
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Leaf07_00EBX
*32 + 17,
// avx512dq
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Leaf07_00EBX
*32 + 18,
// rdseed
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Leaf07_00EBX
*32 + 21,
// avx512ifma
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Leaf07_00EBX
*32 + 28,
// avx512cd
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Leaf07_00EBX
*32 + 29,
// sha
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Leaf07_00EBX
*32 + 30,
// avx512bw
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Leaf07_00EBX
*32 + 31,
// avx512vl
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Leaf07_00ECX
*32 + 1,
// avx512vbmi
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Leaf07_00ECX
*32 + 5,
// waitpkg
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Leaf07_00ECX
*32 + 6,
// avx512vbmi2
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Leaf07_00ECX
*32 + 7,
// shstk
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Leaf07_00ECX
*32 + 8,
// gfni
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Leaf07_00ECX
*32 + 9,
// vaes
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Leaf07_00ECX
*32 + 12,
// avx512bitalg
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Leaf07_00ECX
*32 + 14,
// avx512vpopcntdq
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Leaf07_00EDX
*32 + 15,
// hybrid
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Leaf07_00EDX
*32 + 20,
// ibt
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Leaf07_00EDX
*32 + 23,
// avx512fp16
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Leaf07_01EAX
*32 + 3,
// raoint
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Leaf07_01EAX
*32 + 6,
// cmpccxadd
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Leaf07_01EAX
*32 + 23,
// avxifma
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Leaf07_01EAX
*32 + 26,
// lam
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};
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struct
X86Architecture
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{
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uint64_t
features
;
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char
name
[17 + 1];
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};
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static
const
struct
X86Architecture
x86_architectures
[] = {
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{
cpu_core2
,
"Core2"
},
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{
cpu_westmere
,
"Westmere"
},
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{
cpu_sandybridge
,
"Sandy Bridge"
},
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{
cpu_silvermont
,
"Silvermont"
},
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{
cpu_ivybridge
,
"Ivy Bridge"
},
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{
cpu_goldmont
,
"Goldmont"
},
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{
cpu_haswell
,
"Haswell"
},
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{
cpu_broadwell
,
"Broadwell"
},
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{
cpu_tremont
,
"Tremont"
},
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{
cpu_skylake
,
"Skylake"
},
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{
cpu_skylake_avx512
,
"Skylake (Avx512)"
},
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{
cpu_cascadelake
,
"Cascade Lake"
},
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{
cpu_cooperlake
,
"Cooper Lake"
},
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{
cpu_cannonlake
,
"Cannon Lake"
},
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{
cpu_gracemont
,
"Gracemont"
},
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{
cpu_icelake_client
,
"Ice Lake (Client)"
},
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{
cpu_icelake_server
,
"Ice Lake (Server)"
},
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{
cpu_crestmont
,
"Crestmont"
},
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{
cpu_tigerlake
,
"Tiger Lake"
},
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{
cpu_clearwaterforest
,
"Clearwater Forest"
},
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{
cpu_grandridge
,
"Grand Ridge"
},
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{
cpu_raptorcove
,
"Raptor Cove"
},
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{
cpu_redwoodcove
,
"Redwood Cove"
},
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{
cpu_emeraldrapids
,
"Emerald Rapids"
},
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{
cpu_graniterapids
,
"Granite Rapids"
},
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};
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enum
XSaveBits
{
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XSave_X87
= 0x0001,
// X87 and MMX state
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XSave_SseState
= 0x0002,
// SSE: 128 bits of XMM registers
149
XSave_Ymm_Hi128
= 0x0004,
// AVX: high 128 bits in YMM registers
150
XSave_Bndregs
= 0x0008,
// Memory Protection Extensions
151
XSave_Bndcsr
= 0x0010,
// Memory Protection Extensions
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XSave_OpMask
= 0x0020,
// AVX512: k0 through k7
153
XSave_Zmm_Hi256
= 0x0040,
// AVX512: high 256 bits of ZMM0-15
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XSave_Hi16_Zmm
= 0x0080,
// AVX512: all 512 bits of ZMM16-31
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XSave_PTState
= 0x0100,
// Processor Trace
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XSave_PKRUState
= 0x0200,
// Protection Key
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XSave_CetUState
= 0x0800,
// CET: user mode
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XSave_CetSState
= 0x1000,
// CET: supervisor mode
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XSave_HdcState
= 0x2000,
// Hardware Duty Cycle
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XSave_UintrState
= 0x4000,
// User Interrupts
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XSave_HwpState
= 0x10000,
// Hardware P-State
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XSave_Xtilecfg
= 0x20000,
// AMX: XTILECFG register
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XSave_Xtiledata
= 0x40000,
// AMX: data in the tiles
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XSave_AvxState
=
XSave_SseState
|
XSave_Ymm_Hi128
,
165
XSave_MPXState
=
XSave_Bndregs
|
XSave_Bndcsr
,
166
XSave_Avx512State
=
XSave_AvxState
|
XSave_OpMask
|
XSave_Zmm_Hi256
|
XSave_Hi16_Zmm
,
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XSave_CetState
=
XSave_CetUState
|
XSave_CetSState
,
168
XSave_AmxState
=
XSave_Xtilecfg
|
XSave_Xtiledata
,
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};
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// List of features requiring XSave_AvxState
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static
const
uint64_t
XSaveReq_AvxState
= 0
173
|
cpu_feature_fma
174
|
cpu_feature_avx
175
|
cpu_feature_f16c
176
|
cpu_feature_avx2
177
|
cpu_feature_avx512f
178
|
cpu_feature_avx512dq
179
|
cpu_feature_avx512ifma
180
|
cpu_feature_avx512cd
181
|
cpu_feature_avx512bw
182
|
cpu_feature_avx512vl
183
|
cpu_feature_avx512vbmi
184
|
cpu_feature_avx512vbmi2
185
|
cpu_feature_vaes
186
|
cpu_feature_avx512bitalg
187
|
cpu_feature_avx512vpopcntdq
188
|
cpu_feature_avx512fp16
189
|
cpu_feature_avxifma
;
190
191
// List of features requiring XSave_Avx512State
192
static
const
uint64_t
XSaveReq_Avx512State
= 0
193
|
cpu_feature_avx512f
194
|
cpu_feature_avx512dq
195
|
cpu_feature_avx512ifma
196
|
cpu_feature_avx512cd
197
|
cpu_feature_avx512bw
198
|
cpu_feature_avx512vl
199
|
cpu_feature_avx512vbmi
200
|
cpu_feature_avx512vbmi2
201
|
cpu_feature_avx512bitalg
202
|
cpu_feature_avx512vpopcntdq
203
|
cpu_feature_avx512fp16
;
204
205
// List of features requiring XSave_CetState
206
static
const
uint64_t
XSaveReq_CetState
= 0
207
|
cpu_feature_shstk
;
208
209
struct
XSaveRequirementMapping
210
{
211
uint64_t
cpu_features
;
212
uint64_t
xsave_state
;
213
};
214
215
static
const
struct
XSaveRequirementMapping
xsave_requirements
[] = {
216
{
XSaveReq_AvxState
,
XSave_AvxState
},
217
{
XSaveReq_Avx512State
,
XSave_Avx512State
},
218
{
XSaveReq_CetState
,
XSave_CetState
},
219
};
220
name
GLuint name
Definition
qopengles2ext.h:156
xsave_requirements
static const struct XSaveRequirementMapping xsave_requirements[]
Definition
qsimd_x86.cpp:215
XSaveBits
XSaveBits
Definition
qsimd_x86.cpp:146
XSave_Xtilecfg
@ XSave_Xtilecfg
Definition
qsimd_x86.cpp:162
XSave_AmxState
@ XSave_AmxState
Definition
qsimd_x86.cpp:168
XSave_Zmm_Hi256
@ XSave_Zmm_Hi256
Definition
qsimd_x86.cpp:153
XSave_X87
@ XSave_X87
Definition
qsimd_x86.cpp:147
XSave_Hi16_Zmm
@ XSave_Hi16_Zmm
Definition
qsimd_x86.cpp:154
XSave_CetUState
@ XSave_CetUState
Definition
qsimd_x86.cpp:157
XSave_HwpState
@ XSave_HwpState
Definition
qsimd_x86.cpp:161
XSave_OpMask
@ XSave_OpMask
Definition
qsimd_x86.cpp:152
XSave_HdcState
@ XSave_HdcState
Definition
qsimd_x86.cpp:159
XSave_AvxState
@ XSave_AvxState
Definition
qsimd_x86.cpp:164
XSave_Ymm_Hi128
@ XSave_Ymm_Hi128
Definition
qsimd_x86.cpp:149
XSave_Bndregs
@ XSave_Bndregs
Definition
qsimd_x86.cpp:150
XSave_Xtiledata
@ XSave_Xtiledata
Definition
qsimd_x86.cpp:163
XSave_SseState
@ XSave_SseState
Definition
qsimd_x86.cpp:148
XSave_UintrState
@ XSave_UintrState
Definition
qsimd_x86.cpp:160
XSave_PTState
@ XSave_PTState
Definition
qsimd_x86.cpp:155
XSave_Avx512State
@ XSave_Avx512State
Definition
qsimd_x86.cpp:166
XSave_CetSState
@ XSave_CetSState
Definition
qsimd_x86.cpp:158
XSave_CetState
@ XSave_CetState
Definition
qsimd_x86.cpp:167
XSave_PKRUState
@ XSave_PKRUState
Definition
qsimd_x86.cpp:156
XSave_MPXState
@ XSave_MPXState
Definition
qsimd_x86.cpp:165
XSave_Bndcsr
@ XSave_Bndcsr
Definition
qsimd_x86.cpp:151
x86_locators
static const uint16_t x86_locators[]
Definition
qsimd_x86.cpp:71
X86CpuidLeaves
X86CpuidLeaves
Definition
qsimd_x86.cpp:57
Leaf07_01EAX
@ Leaf07_01EAX
Definition
qsimd_x86.cpp:63
Leaf07_00EDX
@ Leaf07_00EDX
Definition
qsimd_x86.cpp:62
Leaf07_00EBX
@ Leaf07_00EBX
Definition
qsimd_x86.cpp:60
Leaf80000008hEBX
@ Leaf80000008hEBX
Definition
qsimd_x86.cpp:67
Leaf01EDX
@ Leaf01EDX
Definition
qsimd_x86.cpp:58
Leaf07_01EDX
@ Leaf07_01EDX
Definition
qsimd_x86.cpp:64
Leaf80000001hECX
@ Leaf80000001hECX
Definition
qsimd_x86.cpp:66
X86CpuidMaxLeaf
@ X86CpuidMaxLeaf
Definition
qsimd_x86.cpp:68
Leaf13_01EAX
@ Leaf13_01EAX
Definition
qsimd_x86.cpp:65
Leaf07_00ECX
@ Leaf07_00ECX
Definition
qsimd_x86.cpp:61
Leaf01ECX
@ Leaf01ECX
Definition
qsimd_x86.cpp:59
XSaveReq_AvxState
static const uint64_t XSaveReq_AvxState
Definition
qsimd_x86.cpp:172
features_indices
static const uint16_t features_indices[]
Definition
qsimd_x86.cpp:49
x86_architectures
static const struct X86Architecture x86_architectures[]
Definition
qsimd_x86.cpp:118
XSaveReq_Avx512State
static const uint64_t XSaveReq_Avx512State
Definition
qsimd_x86.cpp:192
features_string
static const char features_string[]
Definition
qsimd_x86.cpp:8
XSaveReq_CetState
static const uint64_t XSaveReq_CetState
Definition
qsimd_x86.cpp:206
qsimd_x86_p.h
cpu_haswell
#define cpu_haswell
Definition
qsimd_x86_p.h:163
cpu_feature_avx
#define cpu_feature_avx
Definition
qsimd_x86_p.h:36
cpu_westmere
#define cpu_westmere
Definition
qsimd_x86_p.h:160
cpu_redwoodcove
#define cpu_redwoodcove
Definition
qsimd_x86_p.h:180
cpu_feature_fma
#define cpu_feature_fma
Definition
qsimd_x86_p.h:30
cpu_skylake
#define cpu_skylake
Definition
qsimd_x86_p.h:165
cpu_feature_shstk
#define cpu_feature_shstk
Definition
qsimd_x86_p.h:57
cpu_icelake_server
#define cpu_icelake_server
Definition
qsimd_x86_p.h:173
cpu_feature_avx512ifma
#define cpu_feature_avx512ifma
Definition
qsimd_x86_p.h:47
cpu_gracemont
#define cpu_gracemont
Definition
qsimd_x86_p.h:190
cpu_feature_avx512vpopcntdq
#define cpu_feature_avx512vpopcntdq
Definition
qsimd_x86_p.h:61
cpu_graniterapids
#define cpu_graniterapids
Definition
qsimd_x86_p.h:186
cpu_feature_avx512f
#define cpu_feature_avx512f
Definition
qsimd_x86_p.h:44
cpu_clearwaterforest
#define cpu_clearwaterforest
Definition
qsimd_x86_p.h:194
cpu_icelake_client
#define cpu_icelake_client
Definition
qsimd_x86_p.h:172
cpu_cannonlake
#define cpu_cannonlake
Definition
qsimd_x86_p.h:170
cpu_feature_avx2
#define cpu_feature_avx2
Definition
qsimd_x86_p.h:42
cpu_feature_vaes
#define cpu_feature_vaes
Definition
qsimd_x86_p.h:59
cpu_core2
#define cpu_core2
Definition
qsimd_x86_p.h:77
cpu_feature_avx512vl
#define cpu_feature_avx512vl
Definition
qsimd_x86_p.h:51
cpu_cooperlake
#define cpu_cooperlake
Definition
qsimd_x86_p.h:168
cpu_feature_avx512bitalg
#define cpu_feature_avx512bitalg
Definition
qsimd_x86_p.h:60
cpu_ivybridge
#define cpu_ivybridge
Definition
qsimd_x86_p.h:162
cpu_feature_avx512dq
#define cpu_feature_avx512dq
Definition
qsimd_x86_p.h:45
cpu_grandridge
#define cpu_grandridge
Definition
qsimd_x86_p.h:192
cpu_emeraldrapids
#define cpu_emeraldrapids
Definition
qsimd_x86_p.h:185
cpu_tigerlake
#define cpu_tigerlake
Definition
qsimd_x86_p.h:175
cpu_cascadelake
#define cpu_cascadelake
Definition
qsimd_x86_p.h:167
cpu_tremont
#define cpu_tremont
Definition
qsimd_x86_p.h:189
cpu_feature_f16c
#define cpu_feature_f16c
Definition
qsimd_x86_p.h:37
cpu_feature_avx512vbmi2
#define cpu_feature_avx512vbmi2
Definition
qsimd_x86_p.h:56
cpu_skylake_avx512
#define cpu_skylake_avx512
Definition
qsimd_x86_p.h:166
cpu_feature_avx512fp16
#define cpu_feature_avx512fp16
Definition
qsimd_x86_p.h:66
cpu_feature_avxifma
#define cpu_feature_avxifma
Definition
qsimd_x86_p.h:71
cpu_feature_avx512bw
#define cpu_feature_avx512bw
Definition
qsimd_x86_p.h:50
cpu_sandybridge
#define cpu_sandybridge
Definition
qsimd_x86_p.h:161
cpu_crestmont
#define cpu_crestmont
Definition
qsimd_x86_p.h:191
cpu_goldmont
#define cpu_goldmont
Definition
qsimd_x86_p.h:188
cpu_silvermont
#define cpu_silvermont
Definition
qsimd_x86_p.h:187
cpu_broadwell
#define cpu_broadwell
Definition
qsimd_x86_p.h:164
cpu_raptorcove
#define cpu_raptorcove
Definition
qsimd_x86_p.h:178
cpu_feature_avx512vbmi
#define cpu_feature_avx512vbmi
Definition
qsimd_x86_p.h:54
cpu_feature_avx512cd
#define cpu_feature_avx512cd
Definition
qsimd_x86_p.h:48
X86Architecture
Definition
qsimd_x86.cpp:113
X86Architecture::features
uint64_t features
Definition
qsimd_x86.cpp:114
XSaveRequirementMapping
Definition
qsimd_x86.cpp:210
XSaveRequirementMapping::xsave_state
uint64_t xsave_state
Definition
qsimd_x86.cpp:212
XSaveRequirementMapping::cpu_features
uint64_t cpu_features
Definition
qsimd_x86.cpp:211
qtbase
src
corelib
global
qsimd_x86.cpp
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